These are some Part II project ideas that I've put together. Please contact Tim for more information.

As energy efficiency becomes the main driver for processor development, heterogeneous systems become more seductive compared to their homogeneous counterparts. Heterogeneous systems enable a range of differently-configured cores to match the changing requirements of running programs.

Goal of Project

The goal of this project is to perform an evaluation of a heterogeneous multicore system using the gem5 simulation environment. It can consider a range of cores to determine the optimal system for a group of multithreaded and multiprogrammed workloads. There should not need to be a significant amount of infrastructure development, since gem5 already includes support for multiple, configurable cores. The results will be an analysis of the types of workloads that benefit from heterogeneity in the processor.

Optical network-on-chips are an emerging alternative to current designs, promising extremely low-latency communication between processor cores. However, there are few infrastructures available for evaluation that incorporate processor, memory hierarchy and NoC simulation.

Goal of Project

The goal of this project is to develop the infrastructure for evaluating optical NoCs within the gem5 simulation environment. In particular, the work will consider how to best implement a circuit-switched network in gem5's interconnection network. This will allow evaluation of different topologies (e.g. crossbar and mesh networks) in terms of performance and energy consumption.

Additional Research

As an optional extra, research could consider the types of data that are placed on the optical network and those best suited to a conventional electrical transport.

Hardware caches within a microprocessor consume a significant fraction of the overall chip power budget. One method for reducing their power consumption is to access the caches without doing tag checks when it is known that the required data is already there. This has been successfully applied to the instruction cache, but enabling this in the data cache is still an open research question.

Goal of Project

The goal of this project is to provide an infrastructure for tagless caching within the gem5 simulation environment. There is already an implementation of tagless caching within the classic memory model. The aim is to port this to the Ruby hierarchy, then validate the results of previous work, using existing binaries.

Additional Research

After completing the infrastructure, if desired, research could take the first steps towards tagless data caching. It could start with an analysis of data accesses within a suite of benchmarks, and use this to drive a scheme to lay out the data in a manner suitable for a tagless cache.