Computer Laboratory

Dr. D J Greaves.

Contact details: D J Greaves, MA, PhD, MIET.

Short (auto-)biography: Sep 07
Further photos: A, B, C, D.

David is a Senior Lecturer in Computing Science at the Computer Laboratory and a Fellow of Corpus Christi College .

Consult Google regarding:

Relevant research groups:     Systems Research Group,     Computer Architecture Group,     Programming Research Group,

David Greaves, PhD, MIET, is a University Senior Lecturer interested in compiler and hardware design. He has considerable industrial experience at the CTO/Chief Scientist level and has led the design of many hardware systems, including semi-custom VLSI design.

Lecture Notes: System On Chip Design and Modelling (PDF).

Current Activities:

  • Project spEEDO: Developing a power debug and monitoring API for virtual platforms and real silicon. A continuation of Power estimation from TLM and very-high-level models of computation (VHLS/Prazor). TLM Power 3 Draft User Manual and Download.

  • Algorithm Specification Language: Can a high-level programming expression of an algorithm be seamlessly annotated with implementation aspects concerning hardware structure (e.g. number of RAMs, ALU to operation mapping and level of parallelism) for SMP, FPGA/ASIC and GPU targets? TNDJG:008: Transactional Design Expression (Bluespec/SAFL/TLM) Using Chisel HDL/HCL.

  • Kiwi: Scientific Computing on FPGA (using C# and dotnet DSLs): LINK. FPL Talk (Sept 2014). Comp-Arch Talk (May 2011).

  • Profiles for compositional formal checking: can metadata for system components be digitally signed according to the class of automated checker and checking overhead required when a system is assembled?

Future Activities:

  • Behavioural Machine-Readable Datasheets: CARDs proposal.

  • A new System-Level Description Language (SLDL) for EDA, including the best parts of the H2 temporary language.

  • Draft items, yet to be published: LINK.


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