Bluespec Extensible RISC Implementation (BERI)
|Newflash - October 2013: We have now created a BERI open-source downloads web page that includes links to the hardware specs and build instructions for our Terasic DE4-based tablet, FreeBSD OS support, test suite, and shortly, open-source Bluespec designs.|
|Newsflash - August 2012: BERI support for the FreeBSD operating system has been committed to the FreeBSD Subversion repository, and will be included in FreeBSD 10.0.|
BERI is a soon-to-be-released open source platform to support research into the hardware-software interface, allowing investigation of research questions spanning historically siloed domains in systems research: computer architecture, compilers and programming languages, operating systems, and applications.
The BERI FPGA soft core CPU implements the 64-bit MIPS ISA, and is written in the Bluespec Hardware Description Language (HDL) – a high-level functional programming language for describing hardware designs. Bluespec allows for highly parameterisable designs, as well as easier design-space exploration, making it well-suited for CPU research. Combined with a complete BSD- or Apache-licensed open source software stack, including an adapation of the widely used FreeBSD operating system, Clang and LLVM compiler suite, X.org window system, and applications such as Google's Chromium web browser and the Apache software suite, we are able to perform multi-dimensional systems reseach, exploring complex tradeoffs in via reproducible scientific methodology.
Our first BERI-based research project is CHERI: a research platform deconflating virtualisation and protection; however, the platform is intended to allow exploration of a broad range of other research problems, including in CPU multi-threading, CPU/memory interconnects, tagged memory, compiler-CPU design tradeoffs, CPU extensions for high-performance networking, graphics processing, and many other areas.
We are in the process of open sourcing BERI; you can find more information and download information on the BERI open-source downloads web page. We plan to provide reference bitfiles for Altera FPGAs that may be downloaded and used with supported research, teaching, and evaluation boards from Terasic.
Conference and workshop papers
- Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert Norton, and Michael Roe. The CHERI capability model: Revisiting RISC in an age of risk, Proceedings of the 41st International Symposium on Computer Architecture (ISCA 2014), June 14–16, 2014, Minneapolis, MN, USA.
- Brooks Davis, Robert Norton, Jonathan Woodruff, and Robert N. M. Watson. How FreeBSD Boots: a soft-core MIPS perspective, Proceedings of AsiaBSDCon 2014, 13–16 March, 2014, Tokyo, Japan.
- A Theodore Markettos, Jonathan Woodruff, Robert N. M. Watson, Bjoern A. Zeeb, Brooks Davis, Simon W Moore, The BERIpad tablet: open-source construction, CPU, OS and applications, Proceedings of 2013 FPGA Workshop and Design Contest, November 1st–3rd, Southeast University, Nanjing, China.
- Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Jonathan Anderson, Ross Anderson, Nirav Dave, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Philip Paeps, Michael Roe, and Hassen Saidi, CHERI: A Research Platform Deconflating Hardware Virtualization and Protection, RESoLVE workshop associated with ASPLOS in London, 5–7 March 2012.