CTSRD

Bluespec Extensible RISC Implementation (BERI)

BERI is a soon-to-be-released open source platform to support research into the hardware-software interface, allowing investigation of research questions spanning historically siloed domains in systems research: computer architecture, compilers and programming languages, operating systems, and applications.

The BERI FPGA soft core CPU implements the 64-bit MIPS ISA, and is written in the Bluespec Hardware Description Language (HDL) -- a high-level functional programming language for describing hardware designs. Bluepsec allows for highly parameterisable designs, as well as easier design-space exploration, making it well-suited for CPU research. Combined with a complete BSD- or Apache-licensed open source software stack, including an adapation of the widely used FreeBSD operating system, Clang and LLVM compiler suite, X.org window system, and applications such as Google's Chromium web browser and the Apache software suite, we are able to perform multi-dimensional systems reseach, exploring complex tradeoffs in via reproducible scientific methodology.

Our first BERI-based research project is CHERI: a research platform deconflating virtualisation and protection; however, the platform is intended to allow exploration of a broad range of other research problems, including in CPU multi-threading, CPU/memory interconnects, tagged memory, compiler-CPU design tradeoffs, CPU extensions for high-performance networking, graphics processing, and many other areas.

We are preparing BERI for release as open source in the near future. We also plan to provide reference bitfiles for Altera FPGAs that may be downloaded and used with supported research, teaching, and evaluation boards from Terasic.