Introduction to Computer Architecture Supervision 1

Exercises

1. 2010 Paper 5 Question 2, parts a) and b)
2. 2017 Paper 5 Question 1
3. 2014 Paper 5 Question 1
4. A program requires the following to be executed:
   • 100M integer instructions
   • 75M load/store instructions
   • 30M floating point instructions
   • 12M branch instructions
   A processor has a clock frequency of 3 GHz, and the different instruction types take an average of 1.1, 4.0, 1.6, and 2.1 cycles respectively.
   1. How much does the program speed up if we reduce the CPI of integer instructions to 1.0, and floating point instructions to 1.2?
   2. By how much must we improve the CPI of load/store instructions to get an overall speedup of 1.5?
   3. What is the maximum possible program speedup if we only optimise branch instructions?
5. Is it realistic for a processor to achieve a CPI of less than 1? Justify your answer.
6. Find three CISC instructions which have no equivalent in RISC-V. Describe or give the sequence of RISC-V instructions which would be required to implement the same behaviour.
   Hint: "CISC instruction set" is a generic term which may not give many useful results. You may need to look for a particular one, such as x86, VAX, Z80, etc.