Department of Computer Science and Technology

Technical reports

Three-dimensional integrated circuit layout

Andrew Charles Harter

August 1990, 179 pages

This technical report is based on a dissertation submitted April 1990 by the author for the degree of Doctor of Philosophy to the University of Cambridge, Corpus Christi College.

DOI: 10.48456/tr-202


Some recent developments in semiconductor process technology have made possible the construction of three-dimensional integrated circuits. Unlike other technological developments in two dimensional integration, these circuits present a new and inherently richer connection topology. This offers potential for improved layout in terms of increased density and reduced interconnect length. These circuits will be difficult and expensive to manufacture, at least in the short term, and the scale of the improvement in layout is not apparent. This dissertation presents a discussion of layout and design for three-dimensional integrated circuits.

A number of materials and techniques can be used in the manufacture of such circuits. This choice has a profound bearing on the topology of circuit layout. A classification relating process technolgy to layout topology is developed and illustrated with the design of a number of circuits. A layout system is presented as the vehicle for a series of experiments in three-dimensional layout. It is shown that the system can be constrained to perform circuit layout in a number of topologies in the classification.

Finally, some attempt to quantify the benefits of three-dimensional layout is made. The layout model is calibrated by designing examples of basic circuit elements. This is done using a set of design rules corresponding to a proposed three-dimensional process technology. Circuit layouts produced by the system are compared with conventional two-dimensional layouts, and the variation in layout quality as a function of the three-dimensionality of a layout is explored.

Full text

Only available on paper (could be scanned on request).

BibTeX record

  author =	 {Harter, Andrew Charles},
  title = 	 {{Three-dimensional integrated circuit layout}},
  year = 	 1990,
  month = 	 aug,
  institution =  {University of Cambridge, Computer Laboratory},
  address =	 {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom,
          	  phone +44 1223 763500},
  doi = 	 {10.48456/tr-202},
  number = 	 {UCAM-CL-TR-202}