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Course pages 2021–22

ECAD and Architecture Practical Classes


The ECAD and Architecture Laboratory sessions are a companion to the Introduction to Computer Architecture course. The objective is to provide experience of hardware design for FPGA including use of a small embedded processor. It covers hardware design in SystemVerilog, embedded software design in RISC-V assembly and C, and use of FPGA tools.


This course assumes familiarity with the material from Part IA Digital Electronics, although we will use automated tools to perform many of the steps you might have done there by hand (for example, logic minimisation).

We will be using a Linux command-line environment. We provide scripts and guidance on what you need, however you may find it useful to review Unix Tools, in particular basic navigation such as ls, cd, mkdir, cp, mv. We'll be using the GCC compiler and Makefiles, described in parts 31-32. We will also be using git for revision control and submission of work for ticking - you should review at least parts 23-25 and 29.


The course runs over the 8 weeks of Michaelmas term. The course has been designed so you can do most of the work at home or at any time you wish. You should be able to run all the necessary tools on your own machine, through the use of virtual machines and Docker containers. We have a number of routes to do this in case some of them aren't suitable for the machine you have.

We're running the course in a hybrid mode this year. We will provide online help sessions via Microsoft Teams as well as in-person lab sessions on Fridays and Tuesdays 2-5pm during term.

The core components of the course, being the RISC-V architecture and software and ticked exercise, can be done entirely online, without needing access to hardware. They can be undertaken with any of the platforms we support, including MCS Linux (on the Intel Lab workstations and remotely) if your own machine isn't suitable. We expect everyone to complete these parts.

The rest of the course is optional. The hardware simulation and FPGA compilation can be done on your machine without access to hardware, if you are able to run the virtual machine.

The parts that require access to an FPGA board will need the ability to run the virtual machine and you be able to collect and return an FPGA board from the Department. That process will be described when you come to those parts. There is an optional starred tick available for completion of this part, which will need assessment by a demonstrator in person.

We'll do our best to support all the different platforms and variations, but please bear with us - it's quite possible we'll come across a problem we haven't seen before!

We have provided four routes you can use different tools to complete the course. Some routes necessarily exclude some material but this material is optional.


In a similar way to other practical courses, this course carries one 'tick'. Everyone should expect to receive this tick, and those who do not should expect to lose marks on their final exams.

This year we have adopted the 'chime' autoticker used by Further Java. You will check out the initial files as a git repository from the chime server, commit your work, and push the repository back to submit it. You can then press a button to run tests against your code and the autoticker will tell you whether you have passed. Additionally you may be selected for a (real/video) interview with a ticker to discuss your code and understanding of the material.

Ticking procedures will only be available during weeks 1-8 of Michaelmas term. The deadline for submitting Tick 1 is 5pm on the Tuesday of week 6 (16 November 2021). After passing the autoticker you may be asked for a tick interview with a demonstrator (online or in person). You can gain Tick 1* during the timetabled lab sessions, assuming demonstrators are available.

If you do not submit a successful Tick 1 to the autoticker by 5pm on the Tuesday of week 6 and have a good reason you will need to ask your Directory of Studies to organise an extension. The hard deadline by which all ticks must be completed is noon on Friday 28 January 2022 (the Head of Department Notices is the definitive document). Extensions beyond this date due to exceptional circumstances require a formal application from your college to the Examiners.


While the full course contains 8 exercises, there is not a tight binding to doing one exercise per week. Students should expect to spend about three hours per week on the course, however it is recommended that you make a start on the next exercise if you have time in hand.

Demonstrator help will be focused on the Tuesday and Friday 2-5pm slots during term the lab would normally operate in, so you may find it helpful to work in these times as that will provide the quickest response to questions.


When we have done these labs in person, we have often found they worked well when doing them collaboratively. While your work must be your own, students can work together and help each other, and demonstrators contribute advice and experience with the tools.

For the timetabled sessions, which are Tuesdays and Fridays 2-5pm UK time during term, there will be demonstrators available in the lab and at the same time we'll use the ECAD group on Microsoft Teams. With this we can provide online audio/video help, screensharing and (for the Windows and possibly Mac Teams apps) optional remote control of your development environment. You will be added to the Team in week 1 - if you believe you have been missed please post in the Moodle forum. In Teams there are a number of Helpdesk Channels (A-C) - if you need help during lab times, post in Help Centre and a demonstrator can ask you to go to a specific channel. There are also Student Breakout Channels (D-F) which are available for students to chat amongst themselves.

For help outside of timetabled sessions we've set up a Moodle forum where you can post questions - we'll keep an eye on this at other times, but students are encouraged to use it to support each other.

Students are of course free to use other platforms to help each other. If you find anything useful that we might use in future, please let us know!

If you are having difficulty accessing both Moodle and Teams, please email theo.markettos at


We revise the course each year, which may cause new bugs in the code or the notes. The creators (Theo Markettos and Simon Moore) appreciate constructive feedback.


This course was written by Theo Markettos and Simon Moore, with portions developed by Robert Eady, Jonas Fiala, Paul Fox, Vlad Gavrila, Brian Jones and Roy Spliet. We would like to thank Altera, Intel and Terasic for funding and other contributions.