Course pages 2018–19
ECAD and Architecture Practical Classes
Introduction
The ECAD and Architecture Laboratory sessions are a companion to the Computer Design course. The objective is to provide experience of hardware design for FPGA including use of a small embedded processor.
Scheduling
Laboratory times and signup
Sign-up for the ECAD+Arch Laboratories at the first Computer Design lecture.
Laboratory sessions are timetabled for Tuesday and Friday afternoons. You will sign up for either Tuesday or Friday - you should stick to your slot as we do not have enough capacity to handle more than half the class on a given day. Laboratory sessions are times when you can get expert help and have your work assessed; this is not necessarily the time when you need to complete the work since you can work in other locations. We will allocate hardware to students for the duration of the laboratory sessions (i.e. you get your own kit).
Week 1
Friday/Tuesday of week 1 is the online Verilog tutor (Exercise 0) - you do not need to attend the lab for this session, but demonstrators will be available during the lab to answer any questions and help you if you get stuck.
We also advise making a start on setting up your virtual machine/MCS environment ahead of this session so that demonstrators can help out with any problems you bring along.
Weeks 2-8
The rest of the course consists of Exercises 1-6 - these do not map directly to weeks, so you can proceed at your own pace and should not expect to do exactly one exercise per session. A reasonable expection would be to complete Tick 1 by the end of Week 5, and Tick 2 by Week 8. Equally, if you are less busy towards the start of term it is possible to make progress earlier to reduce your workload later on.
Assessment
There are two ticked exercises with each exercise broken up into smaller, more manageable chunks. Ticks are awarded after demonstrating a working system to a laboratory assessor, and will be awarded during lab time (i.e. until the end of the session in Week 8). Even if you work at home, you will still need to attend some lab sessions for ticking and for demonstrator help: do not assume you can complete the tick work entirely on your own. Speak to a demonstrator if you are having difficulties with the ticked material.
If you have completed a tick, please ask a demonstrator to tick it as soon as possible. The end of term is very busy with ticking and you may have to wait longer to be ticked.
Deadlines
You are required to achieve two ticks. Ticks are only awarded during lab sessions, which are only held in Michaelmas term, hence you need to achieve your ticks by your lab session in Michaelmas week 8. If you are not able to do this for some reason, please speak to your Director of Studies.
For your ticks to be recognised, code and tick questions must be submitted as a portfolio of work by the deadline in early Lent term (see the Head of Department Notices for the definitive date). Each tick describes the materials required - instructions for submission will be emailed in due course.
Laboratory Setup
If you have a suitable laptop we strongly recommend using the ECAD tools in a virtual machine, which will enable you to complete the labs in less time than using the computers in the Intel Lab. Follow the pre-lab setup guide before you arrive for your first session to ensure you have downloaded and configured the virtual machine.
Please note: the tools are quite large, and some install cases benefit from using a 32GB or larger USB stick. If you don't have anything suitable, you may wish to purchase one ahead of time. See the setup guide for details.
- Exercise 0: SystemVerilog web tutor - learn more about SystemVerilog by completing all of our web tutor before starting ticked laboratory sessions.
- Exercise 1: Inputs to the DE1-SoC board - write SystemVerilog to interact with physical inputs to the FPGA and test in simulation.
- Exercise 2: Introduction to FPGA synthesis and the Intel Quartus and Qsys tools
- Optional exercise A: Audio generator in Qsys
- Exercise 3: The Clarvi RISC-V processor
- Exercise 4: Etch-A-Sketch on Clarvi in simulation
- Exercise 5: Clarvi on FPGA
- Exercise 6: Etch-A-Sketch in hardware on the FPGA
Feedback
We revise the course each year, which may cause new bugs in the code or the notes. The creators (Theo Markettos and Simon Moore) appreciate constructive feedback.