Below are some project suggestions by year. Note that projects from earlier years may still be interesting to do.
Project Suggestions for 2013/2014
Explore architectural options to improve the performance of the TTC used in the ECAD+Arch labs. This would include pipelining, use of feed-forward paths and possibly branch prediction and caching.
Bluespec web tutor
Write a web tutor for the Bluespec SystemVerilog language in a similar vein to the SystemVerilog web tutor. Teaching material (examples, etc.) could be taken from the Advanced Computer Design (P34) course.
Vector processing, e.g. for Graphics (challenging/Part III)
Soft vector processors are a promising approach to developing high-performance FPGA applications at a higher level of abstraction than hardware description languages. We have already demonstrated this potential in the area of neural networks (see our 2013 FPL paper about our soft vector processor BlueVec [PDF]), but it would be interesting to see how the idea extends to other application areas such as graphics. This project would involve developing a new soft vector processor (or modifying an existing one) and applying it to a graphics algorithm of your choice.
EDSAC Rebuild Related Project
I'm still interested in the EDSAC rebuild and last year's projects are still an interesting option. I have been doing some work with one of the rebuild volunteers - Bill Purvis - who has built a schematic capture and logic simulator tool in Java which is good for valve circuits. We have been able to automatically convert his netlists into Verilog to allow EDSAC to be simulated/implemented on FPGA. It would be interesting to (a) refine this, and (b) allow test signals to be extracted on a per chassis basis to facilitate test, with the option of outputs from the valves coming back to be checked.
I've never built a relay computer and it sounds like fun! Noisy too! Here is a recent relay computer which is kind of nice though the memory is solid state. One thought would be to do a more theoretical exercise looking at the design of a small processor designed to be efficient in relay logic. Relays could be described in Verilog and simulated or synthesised for FPGA implementation. If time permitted, some section of the machine could be implemented in relays with the rest emulated/implemented in FPGA.
A mechanical memory would also be interesting, but probably well beyond the scope of a Part II project unless somebody has a cunning plan! Konrad Zuse built mechanical memories, e.g. his Z1 computer. Looking at his later machines (Z3 and Z4) might also provide interesting ideas.
Code breaking using an FPGA version of British Turing Bombe
Project Suggestions for 2012/2013
This year I have some projects relating to the EDSAC Replica Project at Bletchley Park.
EDSAC Rebuild - chassis monitor
Build a tPad or DE0-nano based system to monitor an EDSAC chassis. The idea is to have a tiny (e.g. DE0-nano) system in each chassis connected to the test points in order to monitor what the valves are doing. Help can be given to interface the low-voltage FPGA board to the higher voltage chassis. Thought needs to be given to modelling what a chassis does and determining the valid range of signal rise and fall times and the timing relationship between signals. A tPad version with graphical output to help with chassis diagnostics would be desirable and could be considered as an optional extra for the project.
EDSAC Rebuild - cartoon of an EDSAC
The EDSAC rebuild project is focused on a historical recreation of the machine which will be technically interesting but is likely to have little visual appeal for the average punter. As an alternative, a cartoon like machine could be produced which more visually presents the key functional features of the machine. For example, delay-line memories could be modelled using a linear array of LEDs, some visible mechanical oscillation or movement of ball bearings in a clear tube.
Project Suggestions from 2011
I'm principally interested in hardware oriented projects. The kit used in the ECAD+Arch Labs can be used to prototype a huge range of devices. Using an more advanced HDL like Bluespec (see my examples pages) can also speed up development but with some learning cost at the beginning.
Recreate Legacy Processors
Using modern hardware description languages it is now quite tractable to implement legacy processors quickly. How about a SystemVerilog or Bluespec version of a PDP8? Or perhaps a stack machine to execute Forth programs?
The level of difficulty is obviously dependent upon the processor chosen and the existence of tools (instruction set simulator, etc.) that would help development.
Build a GPU capable of the fixed functions in OpenGL 1.1. This is probably too complex unless you're very experienced with Verilog or, better still, already know Bluespec SystemVerilog.
I'd be interested in interfacing the ECAD+Arch Labs board to Lego to replace the Mindstorm controller. This could be an I/O processor coupled to the ARM on the Excalibur part. The ARM would require a library to allow easy configuration of systems. Extensions might be constraint based programming of Lego devices, simulation, etc.