Below is a brief overview of Bluespec examples provided by Simon Moore. It starts with very simple examples and works up to more complex examples showing a range of language features. I hoped that others will find these helpful. I certainly find it very instructive to see longer examples in order to better understand how to structure code. Please note that I was learning the language whilst I went so examples with later dates are likely to be more polished.
Summary of Contents
- Iterative and ROMed versions of Fibonacci functions
- Server Farm
- Module to replicate servers (example of higher-order types)
- VGA and ROM
- Video generation (i.e. time critical Bluespec) and Verilog code encapsulation (FPGA ROM definition)
- NIOS Custom Instruction
- Creating custom instructions for Altera's NIOS processor. Also illustrates passing of interfaces.
- Avalon Streaming
- Bluespec interface to Altera's Avalon Streaming interconnect
- Avalon Master/Slave
- Bluespec interface to Altera's Avalon memory-mapped interconnect. Includes example channel communication for multiple processors.
- Thacker's Tiny Computer 3
- A Bluespec version of Chuck Thacker's Tiny Computer 3 with embedded assembler
Example Systems Running
- Cherry Demo
- Example multi-FPGA board prototype
You are completely free to use these examples. See the license for further details.
In addition, please note that whilst some testing has been performed on all of the examples, I make no guarantees to the correctness of the examples nor that they represent "the best" implementation. They are simply teaching examples.
Many thanks are due to the Bluespec support team for promptly dealing with numerous queries as I learned the language, and to Prof. Joe Stoy for his training. Thanks also to Bluespec for providing licenses for teaching and research. Thanks also to Prof. Arvind for providing examples and allowing me to attend a short course on an early version of Bluespec when I was visiting Prof Asanovic at MIT. It is great to see that Bluespec has evolved into a tool well suited to rapid design of efficient hardware.