Department of Computer Science and Technology

Course pages 2017–18

System on Chip Design and Modelling

This year's exercises will be put online on this page one-by-one.

The deadline timetable is:
Exercise 1 - 29/1/18 12:00
Exercise 2 - 12/2/18 12:00
Exercise 3a - 5/3/18 12:00
Exercise 3b&3c - 16/3/18 12:00
SoC Design & Essay - 24/4/18 16:00

and the structure of the exercises will follow the same pattern as last year, but the topics may be different.

NOTE: Although not assessed, as well as completing these exercises you are expected to have read, some weeks, a paper from the reading list and be ready to lead a short discussion of that paper with the rest of the class.

Moodle Work Submissions

If you are submitting your work via Moodle, this is the LINK.

Assessed Exercises 2017/18

The assessed work consists of Exercises 1, 2 and 3 during the course and a mini-project and structured essay that are to be completed over the Easter Vacation that are largely based on the term-time exercises.

Worksheets for the exercises will be added below. They have target deadlines assigned during the Lent Term. They will be quickly checked/marked and returned to you for possible improvement. Re-submission to get a higher mark is allowed at any point up to the final deadline at the start of the Easter Term.

The total credit available is 100 marks.

For each of exercises 1 to 3, first do the requested practical work sheet. Some questions are provided at the end of each sheet which must each be answered in one or two sentences. Please hand in (or submit via Moodle) a short, formal report to Postgraduate Admin that includes source file listings for files you have created, illustrative output from simulations that demonstrate your result and the answers to the questions. The written part of your report and question answers together should not exceed two pages. The work sheets will be put online, below, about ten days before the work is due to be handed in.

If submitting via hardcopy instead of Moodle, please also email a PDF of your work to DJ Greaves (although do not worry if some figures are missing etc..).

This year hand-in may be via moodle or hardcopy: I will clarify this shortly.

  • Exercise 0: (Christmas Vacation Work): Please ensure you can run the get-you-started "hello world" SystemC example in TOOLINFO Please try to understand every aspect of it and let us know if you foresee any problem. A fairly good knowledge of C++ and the options to the C++ compiler and linker will be needed. Knowledge of makefiles and git will also be helpful. If you have your own machine running 64bit linux then getting SystemC running on that may be useful. Also, please take a good look at the vacation slide pack : VACATION READING. Deadline: Please try to complete in advance of the first practical session. Credit: 0 Marks. Based on the personal email summaries you have already sent, at the first practical session we will review the collective experience of the class to see how much EDA material needs to be formally lectured to you.

  • Exercise 1: Basic RTL I/O device.

    A simple RTL design is provided in Verilog consisting of a pair of communicating components. The task is to re-encode one of the components using RTL-like SYSTEMC. Link to work sheet is HERE. Deadline: 10:00am Mon 29th January: 5 Marks.

  • Exercise 2: TLM version of the basic RTL I/O device.

    In Exercise 2 we make a TLM version of the same component used in Exercise 1. Optionally you should include it in your own copy of Prazor. You will not be able to do the advanced extensions until after we introduce the Prazor Virtual Platform in the 3rd session. Link to work sheet is HERE. Deadline: 10:00am Mon 12th Feb: 5 Marks.

  • Exercise 3a, 3b, 3c: Credit 30 Marks. Link to worksheet HERE

  • Exercise 4a: Credit 30 Marks. Working on your own, properly evaluate and write up your mini-project (or a similar fresh start) developing an an interesting argument that it demonstrates. Further requirements and suggestions are here: HERE.

  • Exercise 4b: Credit 30 Marks. Structured Essay: Use the materials on the reading list, recent articles in Design+Reuse, EDA Cafe and EE Times, the undergraduate lecture notes for System on Chip, the more-advanced slides lectured for P35 and your own research, write an essay following the structure that is precisely defined HERE.