Course pages 2016–17
System on Chip Design and Modelling
Preliminary schedule. Details and credits will be added, but will mostly be the same as last year LINK.
Note that the majority of the credit for this course is allocated to the final Mini-Project and Structured Essay and that Exercise 3 is typically an early demonstration of the Mini-Project.
The timetable for the work items is as follows:
- Preliminary Experience Report (a short email to DJG) - 16th/1/17 12:00
- Exercise 1 - 30/1/17 12:00
- Exercise 2 - 13/2/17 12:00
- Exercise 3a - 6/3/17 12:00
- Exercise 3b&3c - 16/3/17 12:00
- SoC Design Mini-Project & Structured Essay - 25/4/17 16:00
Assessed Exercises 2015/16
NOTE: As well as completing these exercises you are expected to have read, some weeks, a paper from the reading list and be ready to lead a short discussion of that paper with the rest of the class.
The assessed work consists of Exercises 1, 2 and 3 during the course and a mini-project and structured essay that are to be completed over the Easter Vacation that are largely based on the term-time exercises.
Worksheets for the exercises will be added below. They have target deadlines assigned during the Lent Term. They will be quickly checked/marked and returned to you for possible improvement. Re-submission to get a higher mark is allowed at any point up to the final deadline at the start of the Easter Term.
The total credit available is 100 marks.
For each of exercises, first do the requested practical work sheet. Some questions are provided at the end of each sheet which must each be answered in one or two sentences. Please hand in a short, formal report to Postgraduate Admin that includes source file listings for files you have created, illustrative output from simulations that demonstrate your result and the answers to the questions. The written part of your report and question answers together should not exceed two pages. The work sheets will be put online, below, about ten days before the work is due to be handed in.
Please also email a PDF of your work to DJ Greaves (although do not worry if some figures are missing etc..).
- Exercise 0: (Christmas Vacation Work): Please ensure you can run the get-you-started "hello world" SystemC example in TOOLINFO systemc-helloworld.zip. Please try to understand every aspect of it and let us know if you foresee any problem. A fairly good knowledge of C++ and the options to the C++ compiler and linker will be needed. Knowledge of makefiles and git will also be helpful. If you have your own machine running 64bit linux then getting SystemC running on that may be useful. Also, please take a good look at the vacation slide pack : VACATION READING. Deadline: Please try to complete in advance of the first practical session. Credit: 0 Marks. Based on the personal email summaries you have already sent, at the first practical session we will review the collective experience of the class to see how much EDA material needs to be formally lectured to you.
- Exercise 1: Basic RTL I/O device.
A simple RTL design is provided in Verilog consisting of a pair of communicating components. The task is to re-encode one of the components using RTL-like SYSTEMC. Link to work sheet is HERE. Deadline: 10:00am Mon 30th January: 5 Marks.
- Exercise 2: Basic RTL I/O device.
We make a TLM version of the same component. Optionally you should include it in your own copy of Prazor. Link to work sheet is HERE. Deadline: 10:00am Mon 13th Feb: 5 Marks.
- Exercise 3a: Group MiniProject Spec: Write up your part of the group mini-project specification as well as its relationship to the whole. Describe your expected outcome in terms of both what we shall learn and what shall be demonstrable. This will be reviewed and approved and become the basis of the final solo mini-project. TASK SHEET.