Computer Laboratory

Course pages 2016–17

System on Chip Design and Modelling

Preliminary schedule. Details and credits will be added, but will mostly be the same as last year (LINK TO BE ADDED SHORTLY).

Note that the majority of the credit for this course is allocated to the final Mini-Project and Structured Essay and that Exercise 3 is typically an early demonstration of the Mini-Project.

The timetable for the work items is as follows:

  • Preliminary Experience Report (a short email to DJG) - 16th/1/17 12:00

  • Exercise 1 - 30/1/17 12:00

  • Exercise 2 - 13/2/17 12:00

  • Exercise 3a - 6/3/17 12:00

  • Exercise 3b&3c - 16/3/17 12:00

  • SoC Design Mini-Project & Structured Essay - 25/4/17 16:00