Computer Laboratory

Course pages 2014–15

System on Chip Design and Modelling

Principal lecturer: Dr David Greaves
Taken by: MPhil ACS, Part III
Code: P35
Hours: 16 (8 lectures + 8 practicals/coursework and research project option)
Prerequisites: Some experience with VHDL/Verilog RTL, Assembler, C++


A current-day system on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. This course covers SoC design and modelling techniques with emphasis on architectural exploration, assertion-driven design and the concurrent development of hardware and embedded software. This is the ‘front end’ of the design automation tool chain. (Back end material, such as design of individual gates, layout, routing and fabrication of silicon chips is not covered.)


All candidates must have a basic knowledge of programming, digital hardware and assembly language programming. Experience with C++ is also highly useful.

  • Low-level modelling and design refactoring: Verilog RTL Design with examples. Simulation styles (fluid flow versus eventing). Basic RTL to gates synthesis algorithm. Using signals, variables and transactions for component inter-communication. SystemC overview. Structural hazards, retiming, refactoring.
  • Design partition, high-level and hybrid modelling: Bus and cache structures, DRAM interface. SoC parts. Design exploration. Hardware/software interfaces and co-design. Memory maps. Programmer's model. Firmware development. Transactional modelling. Electronic systems level (ESL). IP-XACT. Instruction set simulators, cache modelling and hybrid models.
  • Assertions for design, testing and synthesis: Assertion based design: testing and synthesis. PSL/SVA assertions. Temporal logic compilation to FSM. Glue logic synthesis. Combinational and sequential equivalence. High- level Synthesis and Automated Assembly.
  • Power control and power modelling: Power consumption formulae. Pre-layout wiring estimates. Clock gating. Frequency and voltage dynamic scaling.


On completion of this module, students should:

  • be familiar with how complex gadgets, containing multiple processors, such as an iPod or a sat-nav are designed and developed;
  • understand the hardware and software structures used to implement and model inter-component communication in such devices;
  • be fully familiar with SystemC including transactional modelling;
  • have basic experience using temporal logic and assertions;
  • have designed a SoC architecture at a high level of abstraction, to have run at least one application on it and to have studied its power consumption.


The students will attend eight afternoon sessions where they at first repeat demos developed in the lectures and later develop their own version of a SoC in larger, team-based projects. The initial exercise uses Verilog RTL, but everything else is done using SystemC/TLM (GCC/linux). We use a SystemC multi-processor model using a loosely-timed transactional bus model. This, itself, runs Splash benchmarks, user embedded applications and optionally linux. Students can alter the number of cores and bus and cache structures or add their own hardware models, while exploring the power consumption for their chosen embedded operating system and/or application hosted on the SoC.

Practical work

The coursework itself contains a lot of practical project work and this is easy to extend in any relevant direction. Alternatively, the modelling tools could be extended in new directions, such as implementing very-high-level simulation or new new logic synthesis algorithm recently reported in the literature. Very-high-level simulation is a new area, where power estimates and other metrics of interest, such as chip area, are obtained from broad-brush design partition decisions without resorting to detailed implementation.


  • The lectured component is assessed with a combination of written exercises and small-scale practical projects This accounts for 50% of the course credit.
  • Over the Easter vacation, students must complete a SoC design (based on integrating some of the smaller projects already completed) and a research essay (entitled "SoC Design and Modelling") which together account for the second 50% of the course credit.

Recommended reading

Ghenassia, F. (2010). Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer.
Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System design with SystemC. Springer.
OSCI. SystemC tutorials and whitepapers
Lin, Y-L.S. (ed.) (2006). Essential issues in SOC design: designing complex systems-on-chip. Springer.


P35 System on Chip Design and Modelling cannot be taken in conjunction with R207 Language and Concepts in 2012-13.