ECAD and Architecture Practical Classes
Quartus Project Configuration
Setup
Copy your synchronisation module from Lablet 1.1 into the Lablet 1.2 folder. Select Project | Add/Remove Files in Project... in Quartus. Add the synchronisation module to the project. Now click ... and open the hello_world folder and then the synthesis folder. Select All files in the Files of type dropdown. You will find two files:
- hello_world.v
- The root of a hierarchy of machine-generated Verilog files representing your Qsys SoC.
- hello_world.qip
- Lists all of the files implementing the Qsys SoC. Adding this file to your project imports the listed files at compile time.
Add hello_world.qip (but not hello_world.v) to the project. Finally, click OK.
Timing
Looking at the SDRAM specification shows it requires a clock frequency of at least 100MHz. Looking at an Altera tutorial shows there is about 3ns latency between the SDRAM controller on the FPGA and the SDRAM memory itself elsewhere on the board. We will thus need two clocks at 100MHz: one for the system on the FPGA and one for the SDRAM. For the latter, we also need to adjust the clock signal to compensate for the latency between the SDRAM and its controller.
Add a Phase-Locked-Loop (PLL) with two output clocks at 100MHz, setting the Clock phase shift of one clock to -3.00ns (change units from deg to ns).
Instantiation
Open toplevel.sv. Instantiate the PLL you created above, using CLOCK_50 as the input clock and connecting the shifted clock to DRAM_CLK. The non-shifted clock should be used for everything else, and we suggest you call it clk. You should declare a wire to carry this clock.
Use your module from Lablet 1.1 to synchronise each of the buttons and use button 0 as a reset. Note that the reset input to the Qsys module is inverted - it is called rst_n and the _n means negated. The buttons are also inverted (go low when you press them) so assigning a synchronised button to rst_n without inverting anything is appropriate.
Back in Qsys, go to the HDL Example tab to show a partially complete instantiation of the root module for your SoC. Click the Copy button and paste the example code into toplevel.sv. Complete the example to connect the peripherals, clock and reset; the result should look something like the following:
Compilation
Now compile your Quartus project and program the tPad as you did in Lablet 1.1.