ECAD and Architecture Practical Classes
Synthesis
You should now be able to compile the project and use it to program the tPad.
Compilation
Select Processing | Start Compilation to compile the project (alternatively, press Ctrl + L). If asked to save toplevel.sv before continuing, click Yes. During compilation it is almost certain that warnings will appear in the messages pane at the bottom of the screen. You should always read these through carefully since they can sometimes help you find bugs in your project much faster than waiting for them to manifest. However, due to the unfortunate design of the tools, most of the warnings will be of no consequence and can be safely ignored. As a guide there were 434 warnings at this stage when the demonstrators compiled this project. Significantly more warnings probably means that you forgot to import the pin assignments. If there are any warnings about licensing, call a demonstrator for help.
Timing Analysis
A hardware clock is a signal (square wave) generated by an analogue oscillator. Quartus can infer which wires in your design, such as CLOCK_50, will carry a clock signal based on how they are used in the HD. Each combinational path between two registers has a maximum update latency; for each clock wire, the longest combinational path between the registers it controls dictates the maximum frequency of the oscillator that may be used to drive it. If an oscillator has a higher frequency than this, it is said that the design "does not meet timing," and it is unlikely to work.
Select the Compilation Report tab and expand TimeQuest Timing Analyzer. Expand the Slow 1200mv 85C and Slow 1200mv 0C models and check the Fmax Summary; frequencies above 50MHz indicate it is safe to use the 50MHz oscillator on the board, as defined in the pin assignments you imported. Each model accounts for different latencies due to operating temperature (0C/85C) and manufacturing variations (Slow/Fast).
Timing analysis is improved using a Synopsys Design Constraints file (such as toplevel.sdc) to describe the oscillator(s) driving the wires used as clocks in your design. This allows Quartus to generate a critical warning if an oscillator frequency exceeds the corresponding Fmax. Note that Quartus will still finish compilation and allow you to program the FPGA even if a design fails to meet timing. If a design doesn't work on the FPGA, check if there are any timing warnings, as well as other warnings that could indicate HDL bugs.
Programming
Next, ensure your tPad is connected to the power supply and that the power supply is plugged into a mains socket and turn it on. The row of red LEDs on the back of the board should illuminate dimly and the blue LED next to the power socket should turn on. If not call a demonstrator for help. Ensure SW19 (to the left of the row of switches) is set to RUN. This prevents accidental programming of the flash chip (a separate process to what follows).
Using the USB socket labelled BLASTER (nearest to the power socket, not the socket labelled DEVICE), connect the tPad to your computer.
Select Tools | Programmer, and at the top make sure USB-Blaster ... appears next to Hardware Setup.... If not, click on Hardware Setup..., double click USB-Blaster ... in the list box and then click Close. If the USB Blaster does not appear, call a demonstrator for help.
In the list box, you should see the File toplevel.sof. This is the file that was compiled by Quartus and that we are going to use to program the FPGA. If it is not there, click Add File... and select it from the dialog box that opens. Click Start to program the FPGA. After a few seconds you should see the LEDs on the board flashing. If this doesn't happen, check the warnings that Quartus produced during compilation. If the seven-segment displays are displaying and odd pattern this means that you forgot to import the pin assignments.