Course pages 2012–13
System on Chip Design and Modelling
Assessed Exercises 2012/13
NOTE: As well as completing these exercises you are expected to have read each week a paper from the reading list and be ready to lead a short discussion of that paper with the rest of the class.
The assessed work consists of Exercises 1 to 4 listed below, which have target deadlines assigned during the Lent Term and a mini project and structured essay that may be completed over the Easter Vacation. Exercises 1-4 will be quickly marked and returned to you during term. Re-submission to get a higher mark is allowed at any point up to the final deadline at the start of the Easter Term.
The total credit available is 100 marks.
For each of exercises 1-4, first do the requested practical work sheet. Some questions are provided at the end of each sheet which must each be answered in one or two sentences. Please hand in a short report to Postgraduate Admin that includes source file listings for files you have created, illustrative output from simulations that demonstrate your result and the answers to the questions. The written part of your report and question answers together should not exceed two pages. The work sheets will be put online, below, about ten days before the work is due to be handed in.
- Exercise 0: (Christmas Vacation Work): Please ensure you can run the get-you-started "hello world" example in TOOLINFO. Please try to understand every aspect of it and let us know if you foresee any problem. A fairly good knowledge of C++ and the options to the C++ compiler and linker will be needed. Knowledge of makefiles and CVS will also be helpful. If you have your own machine running 64bit linux then getting SystemC running on that may be useful. Also, please take a good look at the vacation slide pack : VACATION READING. Deadline: Please try to complete in advance of the first practical session. Credit: 0 Marks.
- Exercise 1: Basic RTL I/O device.
A simple RTL design is provided in Verilog consisting of a pair of communicating components. The task is to re-encode one of the components using RTL-like SYSTEMC. Link to work sheet is HERE. Deadline: 10:00am Weds 30th January 2013: 5 Marks.
- Exercise 2: TLM model of same I/O device and rough design of an on-chip message passing API.
The design from exercise 1 is implemented again in SystemC, but using a transactional modelling style. Link to work sheet is HERE. Deadline: 10:30am Monday 11th February 2013: 5 Marks.
- Exercise 3:
Demonstrate proficiency with the OpenRISC blocking-TLM model by preparing an experiment that can potentially be taken further in Exercise 4. Typically you will implement a basic I/O device, coprocessor or message-passing mechanism as a TLM model and write/port an application program (and any needed device driver) to exercise it. The structure must enable various comparisons to be made, such as altering the number of processor cores used and the relative roles of software and specialist hardware. By starting with the BTLM model you already have the ability to adjust the memory architecture of the system (uniform/non-uniform and organisation of caches). You might also investigate whether to use mutable or imutable datastructures or compare using shared memory (cache-consistent or not) with message passing hardware.
Working in pairs is allowed, with one person writing the application code and the other writing the TLM model or message-passing API etc.. Make it clear who did what. Link to work sheet is HERE. Deadline: 12:00 noon Monday 4th March 2013: 15 Marks.
- Exercise 4: Using the experiment prepared in Exercise 3, or otherwise, make an investigation of performance, power, area or other trade offs. Link to work sheet is HERE. Deadline: 12:00 noon Friday 8th March 2013: 15 Marks.
- Exercise 5: Mini-Project Specification
Please submit your plans and progress so far for your mini-project. These should have been discussed with D Greaves in advance. Link to work sheet HERE. Deadline: 10:00am Thurs 14th March 2013: 0 Marks.
- Easter Vacation: Mini-Project and Structured Essay
Mini-Project: Conduct novel practical work according to the specification agreed in Exercise 5 and write it up in a style suitable for publication in Electronics Times or Design and Reuse. Credit 35 Marks.
Research Essay: Title 'SoC Design and Modelling'. Write a research essay strictly according to the provided structure that uses the mini-project as a worked example as much as possible. Credit 25 Marks.
Link to work sheet is HERE.
Deadline: Both due first day Easter Full Term, Tuesday 23rd April 2013. Collaborating is not allowed for the Research Essay and is only allowed for any parts of the mini-project that are borrowed from the term-time work or with express permission that will only be granted if the nature of the collaboration will enable individual contributions to be clearly discriminated.
© David Greaves 2013.