ECAD and Architecture Practical Classes
Quartus Project Configuration
Setup
Navigate to mandelbrot | synthesis in your project directory:
- mandelbrot.v
- The root module of the hierarchy represented by your Qsys system.
- mandelbrot.qip
- Describes the files implementing the Verilog hierarchy generated by a Qsys project.
Add mandelbrot.qip to your Quartus project from the Project menu. Also add your synchronisation module from Lab 1.
Timing
This project has several components with conflicting timing constraints; some components take an additional clock input and contain logic to mediate between two timing domains:
- SDRAM
- Looking at the SDRAM specification shows it requires a clock frequency of at least 100MHz.
- System
- The SDRAM controller requires the system clock match the SDRAM clock; the phase of one of these must be shifted, as described by an Altera tutorial.
- LCD
- The LCD specification requires a 40MHz clock; the controller accepts the LCD clock as an additional input.
- TTC Core
- The implementation of the TTC used in the labs has long combinational paths through the ALU, restricting its Fmax to less than 100MHz. The ring processor component accepts an additional input clock for the TTCs; we'll use the 50MHz clock provided by the project pin assigments.
Add a Phase-Locked-Loop (PLL) with three output clocks:
- c0
- The system clock at 100MHz.
- c1
- The SDRAM clock at 100MHz, with a Clock phase shift of -3.00ns (change units from deg to ns).
- c2
- The LCD clock at 40MHz.
Instantiation
Open toplevel.sv. Instantiate the PLL you created above, using CLOCK_50 as the input clock, connecting c1 to DRAM_CLK and c2 to HC_NCLK. Apart from the additional clock input to the ring processor, the system clock should be used for all other components.
Use your module from Lab 1 to synchronise one of the buttons.
Back in Qsys, go to the HDL Example tab to show a partially complete instantiation of the root module for your system. Click the Copy button and paste the example code into toplevel.sv. Complete the example; the result should look something like the following:
Compilation
Now compile your Quartus project and program the tPad as you did in Lab 1.