ECAD and Architecture Practical Classes
Qsys Project Creation
Go File | Save. Call your project mandelbrot and click Save.
Adding Components
Double-clicking a component in the library adds it to the System Contents. Most allow you to setup various parameters prior to insertion; unless stated, these should remain unchanged.
- Clock Source
- One is provided in the default project. A clock source component receives (often external) clock and reset signals to be used within the system. Double click to open the component properties. Set the Clock frequency to 100MHz (the next page explains why).
- NIOS II Processor
- Look under Embedded Prcoessors. Set Reset vector memory and Exception vector memory to Absolute. These give the absolute addresses to which the program counter (PC) is changed when either a reset or exception event occurs. Click Finish.
- JTAG UART
- Look under Interface Protocols | Serial. This provides buffered character streaming to and from the system on the board. This allows interaction with the system via a NIOS II terminal.
- Interval Timer
- Look under Peripherals | Microcontroller Peripherals. This is used to allow accurate measurement of time by providing periodic interrupts.
- SDRAM Controller
- Look under Memories and Memory Controllers | External Memory Interfaces | SDRAM Interfaces . The tPad has two SDRAM chips, external to the FPGA; these are logically combined under a single interface (wires), available via the Quartus pin assignments. The controller provides an interface which you'll make available for connection to the SDRAM pins in the root module of the Quartus project.
- LCD Controller
- Look under System. Drawing a screen of pixels is achieved by direct memory access (DMA) to a framebuffer stored on the SDRAM; the component provides a memory-mapped master interface (wires) for this purpose. The controller is programmed via the slave interface.
- TTC Ring Processor
- Look under System. The component presents a memory-mapped interface (wires) for communication with the FIFOs at the ring endpoints. Set the number of TTCs in the ring to 16; specify the MIF file you created in the simulation exercises as a path relative relative to the directory the Qsys project is saved in.
Connecting Components
Interrupt interfaces are hidden by default. Right click anywhere in the System Contents and go Filter | All Interfaces. In the IRQ column, connect all Interrupt Sender interfaces to the NIOS II Interrupt Receiver interface.
Look in the Export column. Ensure the Clock Input and Reset Input of the system clock are exported. The ring processor and the LCD controller each need two clock inputs: that of the main system and an addional clock described on the next page; export the latter Clock Input interface. Also export the Conduit interface of the SDRAM and the graphics controller. No other interfaces should be exported.
Complete the Qsys interconnect according to the following outline:
- Clocks
- Connect the remaining Clock Input interfaces of each component (that is not a clock source) to the Clock Output interface of the system clock.
- Resets
- Go System | Create Global Reset Network.
- Bus Interconnect
- Connect all Avalon Memory Mapped Slave interfaces to the data master of the NIOS II processor. Also connect the NIOS II instruction master and the graphics controller DMA master to the SDRAM slave.
Bus Configuration
There are now two steps in configuring the Qsys interconnect.
- Address Partitioning
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In the main panel, look in the Base and End columns under the System Contents tab. These show the memory-mapped address ranges for each slave in your system. You need to partition the address space to ensure these ranges do not overlap. Ensure the Base address of the SDRAM is set to zero and click the padlock to lock it there.
A bug in Qsys requires you manually set the Base address of the lcd controller and the ring processor; 0x08000000 and 0x08002000 should work. Now click System | Assign Base Addresses to automatically complete the partitioning.
- Arbitration
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Multiple masters, such as those of the NIOS II and the graphics controller, share or arbitrate authority over a common slave, such as that of the SDRAM; by default each master is assigned an equal quantum in a Round Robbin (RR) scheduling. Right click anywhere in the System Contents and go Show Arbitration Shares.
The lcd controller is I/O bound: the LCD is constantly refreshed using data read sequentially from the framebuffer. Increase to 128 the relative share of the SDRAM slave to the lcd controller's DMA master.
Generation
Click the Generation tab and then click Generate. This produces the Verilog hierarchy represented by your system, including the necessary interconnect logic to make the connections you specified.