Computer Laboratory

ECAD and Architecture Practical Classes

Lablet 2.2 - Architecture

Qsys Architecture Schematic

The architecture to be constructed is an extension of that of Lablet 2.1, replacing the PIOs with a controller for the LCD screen and adding a custom component implementing a processor comprising a number of TTC cores.

Getting Started

You first need to create a new Quartus project using the same procedure as for lablet 1.1; call your directory e.g. ecad_lablet_2_2. Don't forget to copy and include the design constraints file to specify clocks (toplevel.sdc) and import the pin definition file (tPad_pin_assignments.qsf).

Copy the MIF file and TTC core ( from the simulation exercises into your project directory. Also copy the following files:

A controller to allow manipulation of pixels on the tPad LCD.
A SystemVerilog component instantiating a specified number of TTC cores in a switched ring. Each of the cores runs the same specified MIF program binary. The component enables parameters and responses to be addressed for a particular TTC core in the ring.
Describes the TTC Ring as a Qsys component based on its Verilog.
A component packaging the multi-core processor system. A FIFO is used to store input parameters; these are sent around the ring and put on the input stream of a specified TTC. Results output from the TTC cores are sent to a separate FIFO to await retrieval.

Note that these files (lcd_controller.qsys,,, ring_ttc_hw.tcl, lcd_controller.qsys) will all be imported into your mandelbrot Qsys project (on the next page) and should therefore not be added to your Quartus project to avoid duplicates. Duplicate logic may result in errors and longer compile times.

The only files that should be part of your Quartus project are:

  • toplevel.sdc
  • pll.qip
  • mandelbrot/synthesis/mandelbrot.qip - which will be created by Qsys once you've completed the instructions on the next page

Start Qsys by going to Tools | Qsys.

Previous - Lablet 2.1  |  Contents  |  Next