Computer Laboratory

ECAD and Architecture Practical Classes

Lablet 2.1 - Simulation

Modelsim Development Schematic

Simulation uses special debug statements in standard SystemVerilog files otherwise ignored for synthesis. Using Modelsim, this part of the lab involves simulating the TTC processor core described in lectures. In addition to the HDL description of the processor, a test harness is available to run programs under simulation; you will write some TTC assembly, convert it to a compatible binary (machine code) format using an assembler, and test the program binary using the harness.

Programming For The TTC

Before continuing, it is strongly advised you familiarise yourself with the TTC Assembler Guide.

Create a new directory for this lablet, calling it e.g. ecad_lablet_2_1. Download into this directory the following files:

Java assembler for the TTC processor.
SystemVerilog file. Describes an implementation of Thacker's Tiny Computer (TinyComp), a debug module for use in simulation, and various operational constructs.
SystemVerilog file. Describes a test harness (TestTinyComp) for running programs under simulation.
Modelsim script. Invokes simulation under a custom configuration.
TTC assembly. An example TTC program to add two unsigned numbers.

Open a terminal and cd to the directory you created above.

To assemble a program, type java -jar ttcasm.jar <option> <yourfile.asm>, where yourfile.asm contains TTC assembly code. The output of the assembler depends on the option chosen:

A Memory Initialisation File format used by Quartus when running the program as part of synthesised hardware.
A file, in a similar format, used by Modelsim when running the program as part of a TTC simulation.
Displays the program instructions in a verbose form corresponding to the field layout used by the TTC. Labels are resolved to instruction addresses.
Displays a summary of assembler usage.

Assemble the given program using the rmb format.

Contents  |  Next