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ACS P35-11/12 SoC D/M Slide Pack 1.1 (RTL)

  • SoC Design and Modelling
  • Syllabus
  • Classes and Coursework Assessments

    Introduction: What is a SoC ?

  • Introduction: What is a SoC ?
  • Design Flow
  • Design Flow Diagram
  • Levels of Modelling Abstraction

    Register Transfer Language (RTL)

  • Register Transfer Language (RTL)
  • RTL Summary View of Variant Forms.
  • Structural Verilog
  • Structure Flattening
  • 2a/3: Continuous Assignment.
  • 2b/3: Pure RTL : unordered synchronous register transfers.
  • 3/3: Behavioural RTL
  • Elementary Examples
  • Simulation And Synthesis.
  • Synthesisable RTL
  • Synthesis Example
  • Verilog RTL Synthesis Algorithm: 3-Step Recipe
  • Behavioural - `Non-Synthesisable' RTL
  • Further Synthesis Issues
  • RTL Compared with Software
  • RTL Conclusion
  • Simulation
  • Event Driven Simulation
  • Inertial and Transport Delay
  • Modelling Zero-Delay Components - The Delta Cycle
  • Compute/Commit Cycle With Delta Cycles
  • Hazards
  • Example: Sequential Long Multiplication
  • Multiplier Answer
  • Hazards From Array Memories

    Folding, Retiming & Recoding

  • Folding, Retiming & Recoding
  • Critical Path Timing Delay
  • Protocol and Interface
  • Transactional Handshaking
  • Transactional Handshaking in RTL (Synchronous Example)

    Adder & Multiplier Structures.

  • Adder & Multiplier Structures.
  • Adder Build (Synthesis)
  • Kogge Stone adder
  • Subtractor, Equality, Inequality, Shifts
  • Long Multiplication
  • Micro-Architecture for a Long Multiplier
  • Booth's Multiplier
  • Shifters

    Synthesis & Simulation Algorithms:

  • Synthesis & Simulation Algorithms:
  • Toy implementation of EDS RTL Simulator.
  • Non Determinism.
  • Basic RTL Synthesis Algorithm
  • Examples of converstion to binary (bit lane) form