Raw EDS without deltacycles
while (eventlist <> EMPTY) { e = hd eventlist; eventlist = tl eventlist; tnow = e.time; e.net = e.value; for (m in e.net.models) do m.exec() } | EDS kernel with pending queue:
while (eventlist<>EMPTY) { e = hd eventlist; if (e.time > tnow) and (pending<>EMPTY) { // Commit pendings and commence new delta cycle for (net in pending) do net.current=net.next; pending = EMPTY; for (n in nets just updated) for (m in n.models) m.exec(); } else { tnow = e.time; e.net = e.value; eventlist = tl eventlist; for (m in e.net.models) do m.exec() } } |
Zero-delay models generate new events at the current time, tnow. To avoid shoot-through, these need to be delayed until all current evaluation is complete.
All three of VHDL, Verilog RTL and SystemC support the compute/commit paradigm (also known as evaluate/update) using delta cycles.
Delta cycle: a complete compute/commit cycle that does not advance global time.
Summary algorithm: