Synthesis & Simulation Algorithms:

Toy versions of two RTL processing algorithms are described in this section:

• (EDS) Event-driven simulation,
• Gate-level synthesis.

Gate-level generator code for multipliers, adders, shifters, checkers and other low-level operators is given elsewhere.

datatype m_t = M_AND | M_OR | M_INV | M_XOR | M_DFF | M_BUFIF | M_TLATCH | M_CLOCK;

datatype internal_state_t =
  IS_NONE
| IS_DFF of value_t ref
| IS_CLOCK of int ref
;


and
  model_t = MODEL of string * int * m_t * net_t list * internal_state_t
;

This form of model requires the leaf components (gates) to be built in to the simulator with hard-coded behaviour.

Another form of model, derived originally from Simula in the 1960s, uses user-coded leaf models to be implemented using an imperative language that is interpreted by the simulator.

Verilog RTL supports both built-in gate models and modelling with behavioural threads. par SystemC has no built-in models.