Research Group
I'm lucky enough to work with a range of fantastic people here in the Computer Lab on a variety of research themes. My current research group members are:
- Theodore Markettos (Senior PostDoc)
- Theo has a wide range of interests in electronics, hardware, architecture and operating systems. He is particularly interested in I/O and its security implications, is author of Thunderclap and co-leads the CAPcelerate and IOSec projects.
- Paul Metzger (PostDoc)
- Paul is working on the CAPcelerate project, looking at how we can incorportate CHERI capabilities into future accelerators, as well as how CPUs integrating CHERI can mix with accelerators without support for capabilities.
- Minli Liao (PostDoc)
- Minli works on reliability for multicore processors, implementing efficient hardware schemes for error detection and correction in commodity systems. She is considering high-performance server processors with both homogeneous and hetrogeneous cores in.
- Jianyi Cheng (PostDoc)
- Jianyi works on the CAPcelerate project, which exploits hardware security between CPUs and accelerators. His research aims to produce smaller, faster and more secure hardware with the help of formal methods. His research interests include hardware security, high-level synthesis, formal methods and deep learning.
- Aida Miralaei (PhD Student)
- Aida's PhD is on processing-in-memory for machine learning algorithms. In particular, she is looking at moving the inference phase of binarised convolutional neural networks into DRAM.
- Joe Isaacs (PhD Student)
- Joe is working on techniques to pass semantic information from programmer to compiler and then static analysis that uses this to break data dependences.
- Peter Zhang (PhD Student)
- Peter is working on efficient soft-error detection techniques for legacy binaries, especially through binary modification. His work aims to take advantage of parallelism to keep performance overheads low.
- Matthew Naylor (Senior PostDoc)
- Matthew likes experimenting with new computer architectures using FPGAs. He currently works on the CAPcelerate project, focusing on the interaction between SIMT microarchitecture and the CHERI instruction set extension. He is also interested in functional programming, hardware description languages and property-based testing.
- Zhe (Hugo) Jiang (PostDoc)
- Hugo's current research is looking into run-time hardware support for processor security with the trade-off of real-time performance. His research interests also cover systems architecture and micro-architecture for safety- and security-critical systems. Before joining the University of Cambridge, he received his PhD from the University of York and worked as an R&D and architect at Arm and Renesas Electronics.
- Utpal Bora (PostDoc)
- Utpal is working on the ParaSol project, exploring new static analyses and program transformations to extract fine-grained parallelism. He has worked on bug detection in shared-memory parallel programs using static techniques. His research interests also include performance engineering, automatic vectorization, developing diagnostic tools for HPC, and polyhedral compilation techniques.
- Alex Chadwick (PostDoc)
- Alex is working on the ParaSol project, characterising applications to identify opportunities to extract fine-grained parallelism. His research interests include novel computer architecture and microarchitecture, and compiler and programming language support for targeting to them. He previously worked on hardware and compiler design for the Loki processor, a many-core academic test-chip that was taped out in 2019.
- Mahwish Arif (PhD student)
- Mahwish is investigating static and runtime techniques to improve applications' performance on multi/many-core processors as well as enhancing their security properties.
- Márton Erdős (PhD Student)
- Márton's research is looking into hardware support for fine-grained parallelism, including microarchitectures and speculation. He has previously worked on the Janus binary paralleliser and developed techniques for use-after-free mitigation.
- Yuxin Guo (PhD Student)
- Yuxin works on hardware support for fine-grained task-level parallelism, including transparently extracting parallelism and efficient microarchitectures. He previously worked on projects related to PIM (processing in memory) and is also interested in microarchitectures that reduce the memory wall for general purpose workloads.
Vacancies
I generally take on one or two bright and enthusiastic people to join my group each year. If you are looking to do a PhD with me, I've prepared a page to give some information about the application. I typically advertise postdoc opportunities as they arise, both on the main page and on my Twitter account.
Previous Group Members
I'm always sorry when someone leaves the group, but pleased for them that they can spread their wings and explore pastures new! Here's a list of my not-forgotten research group members and where they headed:
- Jasmin Jahić
- Was PostDoc, went to Arm. Jasmin worked on Janus binary paralleliser and static binary analysis to ensure code is vector-length agnostic.
- Nandor Licker
- Was PhD student, went to SiFive. Nandor studied low-level compiler analysis and optimisation, in particular for creating optimised binaries based on two or more source languages.
- Tobias Kohn
- Was PostDoc, went to Utrecht University. Tobias studied optimisations in Python, particularly ways in which parallelism could be exploited.
- Sam Ainsworth
- Was PhD student, then PostDoc, went to the University of Edinburgh as a lecturer. Sam worked on data prefetching through indirect memory accesses, reliability and security techniques in both hardware and software.
- Peng (Tom) Sun
- Was PhD student, went to Arm. Tom worked on speculative vectorisation hardware.
- Ruoyu (Kevin) Zhou
- Was PhD student, then PostDoc, went to Huawei. Kevin developed the Janus automatic binary parallelisation tool.
- Hsi-Ming Ho
- Was PostDoc, went to Sheffield Hallam University as a lecturer. Hsi-Ming brought a theoretical background to the group and worked on static analysis.
- Xiaochun (Dennis) Zhang
- Was PostDoc, went to Arm. Dennis explored the limits of automatic parallelisation within compilers.
- Martijn Bakker
- Was Research Assistant, went to a finance company in London. Martijn worked on the POETS project.
- Jyothish Soman
- Was PhD Student, went to the DTG. Jyothish's investigated methods for continuing processor execution despite permanent errors.
- Negar Miralaei
- Was PhD Student, tragically died shortly before finishing her dissertation. Negar worked on characterising processor ageing and its effect on applications.
- Konstantina Mitropoulou
- Was PostDoc, went to Intel. Konstantina's research explored soft error detection using the compiler.
- Niall Murphy
- Was PhD Student, co-advised with Robert Mullins, went to ARM. Niall was investigating the use of speculation for DoAcross parallelism.
- Vasileios Porpodas
- Was PostDoc, went to Intel. Vasileios developed schemes to improve the coverage of SLP vectorisation.
- Dan Jones
- Was PostDoc, went to the University of Oxford. Dan was looking at accelerating graph computation.
- Amitabha Roy
- Was PostDoc, went to EPFL, now Intel. Amitabha developed a scheme for optimised cache coherence.
- Georgios Tournavitis
- Was PostDoc, went to Intel. George investigated cache coherence optimisations.
Visitors
I welcome visitors to my group for long or short stays, and at times these have led to successful long term collaborations. Here are some of the past visitors to my group in Cambridge:
- Lucía Pons Escat (from Valencia)
- Lucía performed research into memory bandwidth throttling in high-performance machines.
- Bruno Manganelli (from Glasgow)
- Bruno developed automatic software prefetch techniques for linked data structures.
- Alejandro Valero (from Valencia, now at Zaragoza)
- Alex visited twice and worked with me on wearout mitigation schemes for caches.
- Anouk van Laer (from UCL, now at ARM)
- Anouk's research was investigating photonic networks-on-chip.
- Parham Haririan (from Bremen)
- Parham's PhD work looked at dynamic voltage and frequency scaling.