dwc_otg_hcd_ddma.c File Reference

This file contains Descriptor DMA support implementation for host mode. More...

#include "dwc_otg_hcd.h"
#include "dwc_otg_regs.h"

Go to the source code of this file.

Defines
#define	ISOC_URB_GIVEBACK_ASAP
#define	MAX_ISOC_XFER_SIZE_FS   1023
#define	MAX_ISOC_XFER_SIZE_HS   3072
#define	DESCNUM_THRESHOLD   4
Functions
static uint8_t	frame_list_idx (uint16_t frame)
static uint16_t	desclist_idx_inc (uint16_t idx, uint16_t inc, uint8_t speed)
static uint16_t	desclist_idx_dec (uint16_t idx, uint16_t inc, uint8_t speed)
static uint16_t	max_desc_num (dwc_otg_qh_t *qh)
static uint16_t	frame_incr_val (dwc_otg_qh_t *qh)
static int	desc_list_alloc (dwc_otg_qh_t *qh)
static void	desc_list_free (dwc_otg_qh_t *qh)
static int	frame_list_alloc (dwc_otg_hcd_t *hcd)
static void	frame_list_free (dwc_otg_hcd_t *hcd)
static void	per_sched_enable (dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
static void	per_sched_disable (dwc_otg_hcd_t *hcd)
void	update_frame_list (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
void	dump_frame_list (dwc_otg_hcd_t *hcd)
static void	release_channel_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
int	dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
	Initializes a QH structure's Descriptor DMA related members.
void	dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
	Frees descriptor list memory associated with the QH.
static uint8_t	frame_to_desc_idx (dwc_otg_qh_t *qh, uint16_t frame_idx)
static uint8_t	calc_starting_frame (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)
static uint8_t	recalc_initial_desc_idx (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
static void	init_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)
static void	init_non_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
void	dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
	For Control and Bulk endpoints initializes descriptor list and starts the transfer.
static void	complete_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
uint8_t	update_non_isoc_urb_state_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)
static void	complete_non_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
void	dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
	This function is called from interrupt handlers.

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Detailed Description

This file contains Descriptor DMA support implementation for host mode.

Definition in file dwc_otg_hcd_ddma.c.

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Function Documentation

int dwc_otg_hcd_qh_init_ddma	(	dwc_otg_hcd_t *	hcd,
		dwc_otg_qh_t *	qh
	)

Initializes a QH structure's Descriptor DMA related members.

Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.

Parameters:

	hcd	The HCD state structure for the DWC OTG controller.
	qh	The QH to init.

Returns:

0 if successful, negative error code otherwise.

Definition at line 294 of file dwc_otg_hcd_ddma.c.

void dwc_otg_hcd_qh_free_ddma	(	dwc_otg_hcd_t *	hcd,
		dwc_otg_qh_t *	qh
	)

Frees descriptor list memory associated with the QH.

If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.

Parameters:

	hcd	The HCD state structure for the DWC OTG controller.
	qh	The QH to init.

Definition at line 327 of file dwc_otg_hcd_ddma.c.

void dwc_otg_hcd_start_xfer_ddma	(	dwc_otg_hcd_t *	hcd,
		dwc_otg_qh_t *	qh
	)

For Control and Bulk endpoints initializes descriptor list and starts the transfer.

For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.

Parameters:

	hcd	The HCD state structure for the DWC OTG controller.
	qh	The QH to init.

Returns:

0 if successful, negative error code otherwise.

Definition at line 675 of file dwc_otg_hcd_ddma.c.

void dwc_otg_hcd_complete_xfer_ddma	(	dwc_otg_hcd_t *	hcd,
		dwc_hc_t *	hc,
		dwc_otg_hc_regs_t *	hc_regs,
		dwc_otg_halt_status_e	halt_status
	)

This function is called from interrupt handlers.

Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.

Calls transaction selection routines to activate pending transfers.

Parameters:

	hcd	The HCD state structure for the DWC OTG controller.
	hc	Host channel, the transfer is completed on.
	hc_regs	Host channel registers.
	halt_status	Reason the channel is being halted, or just XferComplete for isochronous transfer

Todo:

Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.

Definition at line 1042 of file dwc_otg_hcd_ddma.c.

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