Department of Computer Science and Technology

Course pages 2017–18

Optimising Compilers

Here I'll post a list of questions that have been asked about the course, whose answers may be useful to everyone.

How do you allocate virtual registers to a specific architectural register when using SSA form?

This is shown in the second “Non-Orthogonal Instructions” slide, an example being return values from functions.

Typically, when we are looking at the target architecture, we are able to detect that a certain instruction will write to a given register (i.e. MUL writing to AX). In spite of code being in SSA form, the instruction will still write to it, however the register allocator will be written to take this into account. There are multiple ways to approach this, but in LLVM's case, we tend to deal with it in such a way that the register allocator's data structures take this into account in a way where no SSA register whose live interval overlaps the MUL instruction can be assigned to AX. The liveness of the MUL instruction will be dealt with via the instruction selector issuing a read/write to the register in question when needed.

See the LLVM documentation for a better and more detailed explanation that is LLVM-specific.

Thanks to Domagoj Stolfa for the question and answer.