Department of Computer Science and Technology

Course pages 2017–18

ECAD and Architecture Practical Classes

Documentation of shift register required to read buttons and other inputs

The display board attached to the DE1-SoC has a number of buttons and other inputs (see right).

Due to a lack of pins available between the display board and the DE1-SoC, these inputs are connected to a shift register that allows them to be read serially.

We use two 74HC165 shift register chips (data sheet). The schematic diagram shows how we have connected them in series. The shift register function table and internal schematic are shown separately. (Internals (c) NXP and TI datasheets)

Each button is active low (ie a push of the 'A' button causes BUTTON_A to go from high to low and then back to high again when released). The output of the shift register is inverted, so the bits received by the FPGA are active high (so we refer to BUTTON_A in the code).

The shift register can be read in the FPGA using the module.

The following code with convert the buttons[15:0] into meaningful names:

typedef struct packed {
	logic button_b;
	logic button_a;
	logic button_y;
	logic button_x;
	logic spare0;
	logic touch_irq;
	logic spare1;
	logic spare2;
	logic nav_u;
	logic nav_l;
	logic nav_r;
	logic nav_d;
	logic nav_click;
	logic dialr_click;
	logic diall_click;
	logic temperature_alarm;
} buttonsT;

buttonsT buttons_decoded;

always_comb begin
	buttons_decoded = buttons;
	// access fields as eg buttons_decoded.dialr_click