Computer Laboratory

Course pages 2013–14

System-on-Chip Design and Modelling

Slides by Subject Group

Slides will be added as we go.

Note layout varies slightly from the printed notes.

  • Introduction: SLIDES.

  • SG1: SLIDES RTL. Verilog RTL design with examples. Event-driven simulation with and without delta cycles, basic gate synthesis algorithm and design examples. Structural hazards (memories and multipliers) Pipelining and handshake synthesis. [3 lectures]

  • SG2: Basic SystemC. Using SystemC instead of Verilog. Nets conveying abstract data types for higher-level modelling. [1 Lecture]

  • SG3:SLIDES SOCPARTS (not all will be used - DRAM and Cache not lectured this year). Basic bus structures. Bus structure. I/O device structure. Interrupts, DMA and device drivers. Examples. Basic bus bridging.

  • SG4:SLIDES ESL. ESL + transactional modelling. Electronic systems level (ESL) design. Architectural exploration. Firmware modelling methods. Blocking and non-blocking transaction styles. Approximate and loose timing styles. [1 lecture]

  • SG5:SLIDES ABD. Assertion-based design (ABD): assertions and monitors. Types of assertion (imperative, safety, liveness, data conservation). PSL/SVA assertions. Temporal logic compilation of fragments to monitoring FSM. [1 lecture]

  • SG6:SLIDES TTE. (None of the tools were lectured this year).


Course Materials: Lecture Notes and Exercise Sheets

Additional Materials

Documents and Reference Materials

Online Try-it-yourself Experiments

Running the cv2 simple RTL compiler

Login to the PWF using, for instance,


Set up the following environment variables:

export PATH=/ux/clteach/djg11/cv2.18:$PATH
export CVPATH=.:/ux/clteach/djg11/cv2.18/libs

Compile a test file as follows:

cp /ux/clteach/djg11/cv2.18/tests/test.v .
cv2 -root TEST -vnl test.v

Then edit test.v according to your own interests and compile again.

An old cv2 user manual is here (PDF).

Lecture Timetable

This timetable will be updated regularly to reflect the pace achieved.

  • Lecture 1: F 11th Oct: Introduction. Then start of SG1 - RTL/Verilog.

  • Lecture 2: M 14th Oct: SG1 - RTL/Verilog - continued...

  • Lecture 3: W 16th Oct: SG1 - RTL/Verilog - continued...

  • Lecture 4: F 18th Oct: SG1 - RTL/Verilog - finished.

  • Lecture 5: M 21st Oct: SG2 - Basic SystemC

  • Lecture 6: W 23th Oct: SG3 - SoC Parts.

  • Lecture 7: F 25th Oct: SG3 - SoC Parts continued...

  • Lecture 8: M 28th Oct: SG3 - SoC Parts finished (cache and DRAM slides not used).

  • Lecture 9: W 3th Oct: SG4 - ESL.

  • Lecture 10: F 1st Oct: SG5 - ESL finished, ABD started.

  • Lecture 11: M 4th Oct: SG6 - ABD finished. Technology part of TTE.

  • Lecture 12: W 6th Oct: SG7 - Power.

Last year’s course materials are still available.