Course pages 2012–13

System-on-Chip Design and Modelling

Slides by Subject Group

• Introduction: SLIDES.

• SG1: SLIDES RTL. Verilog RTL design with examples. Event-driven simulation with and without delta cycles, basic gate synthesis algorithm and design examples. Structural hazards (memories and multipliers) Pipelining and handshake synthesis. [3 lectures]

• SG2:SLIDES SYSC. SystemC overview. The major components of the SystemC C++ class library for hardware modelling are covered with code fragments and demonstrations. Queuing/contention delay modelling. Power, energy and layout high-level modelling. [2 lectures]

• SG3:SLIDES SOCPARTS (not all will be used). Basic bus structures. Bus structure. I/O device structure. Interrupts, DMA and device drivers. Examples. Basic bus bridging.

• SG4:SLIDES ESL. ESL + transactional modelling. Electronic systems level (ESL) design. Architectural exploration. Firmware modelling methods. Blocking and non-blocking transaction styles. Approximate and loose timing styles. Examples. [2 lectures]

• SG5:SLIDES ABD. ABD: assertions and monitors. Types of assertion (imperative, safety, liveness, data conservation). Assertion-based design (ABD). PSL/SVA assertions. Temporal logic compilation of fragments to monitoring FSM. [1 lecture]

• SG6:SLIDES TTE. The following slides were not covered this year: RAM Macrocell Compiler Tool, Test Program Generator Tool, Scan Path Insertion and JTAG standard test port, Gate Arrays and Field-Programmable Logic, FPGA - Field Programmable Gate Array, PALs and CPLDs Xilinx Zynq Super FPGA. Design Exploration and Engineering aspects: FPGA and ASIC design flow. Cell libraries. Market breakdown: CPU/Commodity/ASIC/FPGA. Further tools used for design of FPGA and ASIC (a subset of: timing modelling, place and route, memory generators, clock tree, self-test and scan insertion). [1 lecture max]

• SG7:SLIDES POWER. Silicon Power and Technology: power gating, dynamic frequency and voltage scaling. [1.5 lectures]

• (SG8):SLIDES HLS. Probably no slides will be covered. Higer-level approaches Only presented if time permits. Non-examinable. Co-design, co-synthesis and custom processor synthesis. IP-XACT, Kiwi HLS. Transactor synthesis.

Course Materials: Notes and Exercise Sheets

• Lecture Notes (lightly updated) PDF 130 pages.

• Lecture Notes (as printed) O.

• Exercise Sheet 1 : Short Questions: (PDF).

• Exercise Sheet 2 : Longer Questions: (PDF).

• PWF SystemC Classes 1-2.

• PWF Classes 3-6

• Ethernet CRC Example.

Additional Materials

• Folder containing tarball of VHLS OpenRISC simulator using TLM2.0 sockets (if you really want to get your hands dirty) distribution.

Lecture Timetable

This is a provisional timetable that will be updated regularly to reflect the pace achieved.

• Lecture 1: Introduction. Then start of SG1 - RTL/Verilog.

• Lecture 2: SG1 continued.

• Lecture 3: SG1 concluded.

• Lecture 4: SG2 - SystemC Overview.

• Lecture 5: SG3 Bus Structures.

• Lecture 6: SG3 second third lectured.

• Lecture 7: F 10th May: SG3 conclusion. SG4 - ESL and TLM Modelling.

• Lecture 8: M 13th May: SG4 concluded.

• Lecture 9: W 15th May: SG5 - ABD

• Lecture 10:F 17th May: SG6 - Engineering Aspects.

• Lecture 11:M 20th May: SG6 concluded.

• Lecture 12:W 22nd May: SG7 - Silicon Power and Technology.

• Examples class(es): date(s) to be set.