Course pages 2011–12

Computer Design

Principal lecturer: Dr Simon Moore
Taken by: Part IB
Past exam questions: Computer Design, ECAD
Information for supervisors (contact lecturer for access permission)

Errata on Lectures

See the materials page.

Addendum to the syllabus

This course has been overhauled this year and there have been some minor adjustments to the syllabus (below) that was prepared earlier in the year:

An implementation of the Manchester Baby machine has been dropped in favour of introducing the implementation of Chuck Thacker's Tiny Computer 3 used in the ECAD+Arch labs. This new lecture is listed on the syllabus as "Building a simple RISC machine".
Due to the above change, there are now only 17 lectures. The spare lecture slot has been left available in case there is a major problem with the new ECAD+Arch labs which requires additional support teaching.
The SystemVerilog FPGA design lecture has been swapped with the Chip, board and system testing lecture.

The syllabus

No. of lectures: 22 (including 4 via a web-based tutor)
Prerequisite course: Digital Electronics
This course is a prerequisite for the Part II courses Comparative Architectures and System-on-Chip Design.

Aims

The aims of this course are to introduce a hardware description language (SystemVerilog) and computer architecture concepts in order to design computer systems. This is an amalgam of the former ECAD and Computer Design courses.

There are 18 lectures which cover design with hardware description languages, computer architecture and then computer implementation. A web based tutor (equivalent of 4 lectures) is used to teach much of the SystemVerilog hardware description language.

Lectures

Introduction and motivation. Current technology, technology trends, ECAD trends, challenges.
Logic modelling, simulation and synthesis. Logic value and delay modelling. Discrete event and device simulation. Automatic logic minimization.
SystemVerilog FPGA design. Practicalities of mapping SystemVerilog descriptions of hardware (including a processor) onto an FPGA board. Tips and pitfalls when generating larger modular designs.
Chip, board and system testing. Production testing, fault models, testability, fault coverage, scan path testing, simulation models.
Historical perspective on computer architecture.
Early instruction set architecture. EDSAC versus Manchester Mark I.
Build your first computer. Implement a Manchester Baby machine in Java and SystemVerilog.
RISC machines. Introduction to RISC processor design.
Building a simple RISC machine.
CISC machines and the Intel x86 instruction set.
Java Virtual Machine.
Memory hierarchy. Caching, etc.
Hardware support for operating systems. Memory protection, exceptions, interrupts, etc.
Pipelining and data paths.
Internal and external communication.
Introduction to many-core processors.
Data-flow machines. Future directions.

On-Line Learning Component: Cambridge SystemVerilog Tutor

The interactive web-based tutor teaches the synthesizable subset of SystemVerilog which is required to complete the laboratory sessions.

Objectives

At the end of the course students should

be able to read assembler given a guide to the instruction set and be able to write short pieces of assembler if given an instruction set or asked to invent an instruction set;
understand the differences between RISC and CISC assembler;
understand what facilities a processor provides to support operating systems, from memory management to software interrupts;
understand memory hierarchy including different cache structures;
appreciate the use of pipelining in processor design;
understand the communications structures, from buses close to the processor, to peripheral interfaces;
have an appreciation of control structures used in processor design;
have an appreciation of how to implement a processor in SystemVerilog.

Computer Laboratory