Together with my colleage Ross Anderson we brought together a research consortium to undertake research into improved physical security for smart cards and similar low cost devices. This work started in April 2000 and finished in January 2003 funded by the European Commission under the 5th Framework programme. The final report is available via www.g3card.org.
Early work was presented at the European Asynchronous Circuits Working Group (ACiD-WG) in early 2000. The abstract is available: Improving Smartcard Security Using Self-timed Circuit Technology.
In 2002 we presented an award wining paper at Async'2002: Improving Smart Card Security using Self-timed Circuits. Later in the year we produced an extended paper for the Microprocessors and Microsystems Journal which extends the earlier work and presents many more results: Balanced Self-Checking Asynchronous Logic for Smart Card Applications.
We also undertook work on attack technologies in order to better evaluate our design work. See the TAMPER Lab pages for further details.
The G3Card project web site is archived here.