SPEAR: Shape-shifting many-core
(The Loki many-core processor)
This 5-year ERC funded project (SPEAR ref:306386) builds upon our experience of designing on-chip networks and previous work on our flexible many-core architecture (Loki). The aim is to investigate the design and implementation of massively-parallel single-chip architectures that place the network at the heart of their design. Our simple cores are far more deeply interconnected to each other than traditional designs, sharing some similarities to FPGAs. The network is also free to carry both instructions and data between cores allowing cores to be exploited using a variety of execution patterns. We are pursuing work both the architecture and circuit levels, together with the development of new compilation tools.
A test-chip with 128-cores (4 x 4 tiles x 8 cores) will soon be fabricated at 40nm.
- Robert Mullins (PI)
- Daniel Bates (RA)
- Alex Bradbury (RA)
- Alex Chadwick
- George Sarbu
- Andreas Koltes (graduated)
Configurable memory systems for embedded many-core processors
Daniel Bates, Alex Chadwick and Robert Mullins
International Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES 4), January 2016.
Exploiting Tightly-Coupled Cores
Daniel Bates, Alex Bradbury, Andreas Koltes and Robert Mullins
Journal of Signal Processing Systems, August 2014.
Loki: A Polymorphic Array of Simple Processors
Daniel Bates, Alex Bradbury and Robert Mullins
HiPEAC Innovation Event, May 2010.
There are currently research
opportunities in this area for potential PhD students.
Previous related funding
EPSRC (EP/G033110/1) from 2009-2013