Course pages 2015–16
ECAD and Architecture Practical Classes
THIS IS IN A DRAFT FORM AS WE COMPLETE THE NEW ECAD+ARCH PAGES
The ECAD and Architecture Laboratory sessions are a companion to the Computer Design course. The objective is to provide experiance of hardware design for FPGA including use of a small embedded processor.
Laboratory sessions are timetabled for Tuesday and Friday afternoons. You will sign up for either Thursday or Friday and you should stick to your slot. Laboratory sessions are times when you can get expert help and have your work assessed; this is not necessarily the time when you need to complete the work since you can work in other locations. We will allocate hardware to students for the duration of the laboratory sessions (i.e. you get your own kit).
This year we are using new hardware and have new laboratory sessions too. The new hardware will only become available part way through Michaelmas term. Please be patient of bugs in the new laboratories and the creators (Simon Moore and Theo Markettos) appreciates constructive feedback.
There are two ticked exercises with each exercise broken up into smaller, more manageable chunks. Ticks are awarded after demonstrating a working system to a laboratory assessor. Code created must be submitted as a portfolio of work by early Lent term (see the Head of Department Notices for the definative date).
- Exercise 0: SystemVerilog web tutor - learn more about SystemVerilog by completing all of our web tutor before starting ticked laboratory sessions.
Signup for the ECAD+Arch Laboratories at the first Computer Design lecture.