Computer Laboratory – ECAD and Architecture Practical Classes: ECAD Lablet 2.2

ECAD and Architecture Practical Classes

Qsys Project Creation

Select File | Save. Call your project mandelbrot and click Save.

Adding Components

Double-clicking a component in the library adds it to the System Contents tab. Most allow you to setup various parameters prior to being added; unless stated, these should remain unchanged. You need to add the following components:

Clock Source: One is provided in the default project. A clock source component receives (often external) clock and reset signals to be used within the system. Double click the Clock Source component in the System Contents tab to open its properties. Set the Clock frequency to 100000000 Hz (100MHz, the next page explains why) and click Finish.
NIOS II Processor: Look under Embedded Processors. Set Reset vector memory and Exception vector memory to Absolute. These give the absolute addresses to which the program counter (PC) is set when either a reset or exception event occurs. Click Finish.
JTAG UART: Look under Interface Protocols | Serial. This provides buffered character streaming between the SoC and the host PC. This allows interaction with the system via a NIOS II terminal.
Interval Timer: Look under Peripherals | Microcontroller Peripherals. This is used to allow accurate measurement of time by providing periodic interrupts.
SDRAM Controller: Look under Memories and Memory Controllers | External Memory Interfaces | SDRAM Interfaces . The tPad has two SDRAM chips, external to the FPGA; these are logically combined into a single interface (wires), available via the Quartus pin assignments. The controller provides an interface which export from the Qsys project for connection to the SDRAM pins in the top-level SystemVerilog file of the Quartus project. Right-click on the SDRAM controller and select Rename. Type sdram_0 and press Enter.
LCD Controller: Look under System. Drawing a screen of pixels is achieved by direct memory access (DMA) to a framebuffer stored in the SDRAM; this component provides a memory-mapped master interface (wires) for this purpose. The controller is programmed via the slave interface.
TTC Ring Processor: Look under System. This component presents a memory-mapped interface (wires) for communication with the FIFOs at the ring endpoints. Set the number of TTCs in the ring to 16; specify the MIF file you created in the simulation exercises as a path relative relative to the directory the Qsys project is saved in. If you saved your MIF file as mandelbrot.mif in the Quartus project directory, you can leave this as it is.

Connecting Components

Interrupt interfaces are hidden by default. Right click anywhere in the System Contents and select Filter | All Interfaces. In the IRQ column, connect all Interrupt Sender interfaces to the NIOS II Interrupt Receiver interface.

Look in the Export column. Ensure the Clock Input and Reset Input of the system clock are exported. The ring processor and the LCD controller each need two clock inputs: the main system clock and an addional clock described on the next page; export the latter Clock Input interface. Also export the Conduit interface of the SDRAM and the graphics controller. No other interfaces should be exported. By default Qsys will export the clk_sys and reset of the LCD controller and the TTC ring - you will need to fix this.

Complete the Qsys SoC as follows:

Clocks: Connect the remaining Clock Input interfaces of each component (that is not a clock source) to the Clock Output interface of the system clock, including the clk_sys and reset inputs of the LCD controller and TTC ring that are incorrectly exported.
Resets: Select System | Create Global Reset Network. You will need to manually connect the LCD controller and TTC ring reset inputs to the reset outputs of both the clock source and the NIOS II JTAG Debug Module as has been done automatically for the other components.
Bus Interconnect: Connect all Avalon Memory Mapped Slave interfaces to the data master port of the NIOS II processor. Also connect the NIOS II instruction master and the graphics controller DMA master to the SDRAM slave.

Bus Configuration

There are now two more steps to finish configuring the Qsys interconnect.

Address Partitioning

In the main panel, look in the Base and End columns under the System Contents tab. These show the memory-mapped address ranges for each slave in your system. You need to partition the address space to ensure these ranges do not overlap. Ensure the Base address of the SDRAM is set to zero and click the padlock to lock it there.

Select System | Assign Base Addresses to automatically complete the partitioning.

Arbitration

Multiple masters, such as those of the NIOS II and the graphics controller, share or arbitrate authority over a common slave, such as that of the SDRAM; by default each master is assigned an equal quantum in a Round Robbin (RR) schedule. Right click anywhere in the System Contents tab and select Show Arbitration Shares.

The LCD controller is I/O bound: the LCD is constantly refreshed using data read sequentially from the framebuffer. Increase the number of arbitrartion shares of the LCD controller's DMA master for the SDRAM slave to 128 by typing 128 in the box at the connection of controller_0_dma.m0 and sdram_0.s0.

Generation

Click the Generation tab and then click Generate. This produces Verilog modules represented by your system, including the necessary interconnect logic to make the connections you specified. Generation should report no errors or warnings. After generation has finished click Close.

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