ECAD and Architecture Practical Classes
Lablet 1.1 - Synthesis
Synthesis is the process of mapping Hardware Description Language (HDL) code, such SystemVerilog, on to the basic units provided by a FPGA e.g. LUTs, wiring, memory etc. You will use the Quartus synthesis tool in these labs. This part of the lab guides you through creating a Quartus project, synthesising HDL and programming and testing it on the FPGA.
Creating a Quartus Project
First, create a new directory for this project in your filespace, perhaps called ecad_lablet_1_1.
Important: Some tools in Quartus do not like paths with spaces in, so ensure all file and directory names you choose do not have spaces in them.
Download the following files into the new directory:
- Top-level SystemVerilog file. Quartus projects use multiple SystemVerilog modules to implement a complete FPGA design. The top-level file contains the module which instantiates all of the other modules and which is used to connect them to the FPGA's pins.
- A design constraints file. Describes the hardware clocks that are connected to the FPGA. Quartus uses information about the clocks to decide if a synthesised design will run correctly or experience timing issues.
- Pin assignments file. To interact with the hardware, this file matches (groups of) pins (e.g. those for the red LEDs) on the device to 'friendly' names (e.g. so the red LEDs can be named LEDR[17:0]) in the top-level SystemVerilog file.
Start Quartus as described at the start of this lab. If Quartus reports any licensing issues here, ask a demonstrator for help.
Once Quartus has started, it should ressemble the screenshot to the right. At the bottom is the Messages pane, which displays compilation messages and warnings; this may be useful when trying to debug your project. On the left is the Project Navigator, the first tab shows the logical hierarchy of the project. Below this the Tasks pane shows the state of compilation.
Create a New Project
Select File | New Project Wizard and click Next to display the screen shown on the right. In the top box, enter the directory where you downloaded the 3 files above. In the second box, enter a name of the project; this can be whatever you like, though we reccommend ecad_lablet_1_1. In the bottom box, type toplevel since this is the name of the top-level SystemVerilog module for this project. Now click Next.
On the next page, click Add All to add the SystemVerilog and SDC files you downloaded earlier into the project. If these files do not appear in the list, ensure you have saved them in the same directory that you specified as the working directory in the previous step. Now click Next.
This page lets you select the type of FPGA used by the project. In the drop down boxes at the top, select family Cyclone IV E, package FBGA, pin count 780 and speed grade 7 and ensure that Specific device selected in 'Available devices' list is selected. Next, in the Available devices list at the bottom, select EP4CE115F29C7. This is the part number of FPGA that is on the tPad board.
Now click Finish to complete project setup.
Import Pin Assignments
You need to import the pin assignments from the .qsf file you downloaded earlier. To do this, select Assignments | Import Assignments... click on the button labelled "..." and select the tPad_pin_assignments.qsf file. Click OK and then click OK again to import the assignments.
Important: Failure to import pin assignments will result in your design not being connected to the outside world. Quartus will optimise it to nothing since it doesn't have any used input and output signals. You must import the pin assignments in every project you create, including new projects in other lablets. Just copying the .qsf file isn't enough.
Quartus uses Verilog 2001 as the default HDL but we'll be using SystemVerilog throughout. Select Assignments | Settings... and then click on Analysis & Synthesis Settings | Verilog HDL Input in the window that opens and then select SystemVerilog. Then click Apply and OK.
Save these changes by selecting File | Save Project.