/*** Quartus Project Root Module *** *** The interface is a subset of the pin assignments *** on the FPGA board. *** ***/ module toplevel ( // clock from external oscillator input CLOCK_50, // LEDs and buttons input [3:0] KEY, output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, output logic [6:0] HEX6, output logic [6:0] HEX7, output logic [7:0] LEDG, output logic [17:0] LEDR, // SDRAM interface output [12:0] DRAM_ADDR, output [1:0] DRAM_BA, output DRAM_CAS_N, output DRAM_CKE, output DRAM_CLK, output DRAM_CS_N, inout [31:0] DRAM_DQ, output [3:0] DRAM_DQM, output DRAM_RAS_N, output DRAM_WE_N, // LCD interface output [5:0] HC_R, output [5:0] HC_G, output [5:0] HC_B, output HC_DEN, output HC_NCLK ); /*** Declare state machine ***/ logic [24:0] counter; always_ff @(posedge CLOCK_50) begin // Display test pattern if (counter == 0) begin LEDR <= ~LEDR; LEDG <= ~LEDG; HEX0 <= ~HEX0; HEX1 <= ~HEX1; HEX2 <= ~HEX2; HEX3 <= ~HEX3; HEX4 <= ~HEX4; HEX5 <= ~HEX5; HEX6 <= ~HEX6; HEX7 <= ~HEX7; end counter <= counter + 1; end endmodule