ECAD and Architecture Practical Classes
Qsys Project Creation
Go File | Save. Call your project hello_world and click Save.
Adding Components
Double-clicking a component in the library adds it to the System Contents. Most also allow you to setup various parameters prior to insertion; unless stated, these should remain unchanged.
- Clock Source
- One is provided in the default project. A clock source component receives (often external) clock and reset signals to be used within the system. Double click to open the component properties. Set the Clock frequency to 100MHz (the next page explains why).
- NIOS II Processor
- Look under Embedded Processors. Set Reset vector memory and Exception vector memory to Absolute. These give the absolute addresses to which the program counter (PC) is changed when either a reset or exception event occurs. Click Finish.
- JTAG UART
- Look under Interface Protocols | Serial. This provides buffered character streaming to and from the system on the board. This allows interaction with the system via a NIOS II terminal.
- Interval Timer
- Look under Peripherals | Microcontroller Peripherals. This is used to allow accurate measurement of time by providing periodic interrupts.
- SDRAM Controller
- Look under Memories and Memory Controllers | External Memory Interfaces | SDRAM Interfaces . The tPad has two SDRAM chips, external to the FPGA; these are logically combined under a single interface (wires), available via the Quartus pin assignments. The controller provides an interface which you'll make available for connection to the SDRAM pins in the root module of the Quartus project.
- PIO (Parallel I/O)s
- Look under Peripherals | Microcontroller Peripherals. A PIO is basically a memory-mapped register of specified width. A connected device having a compatible interface (wires) may read or write this register, according to the type of PIO. We will need two of these: one will allow output to 8 of the red LEDs; another will allow input from 3 of the buttons (we could alternatively have a single-bit PIO for each button).
At this point your project should ressemble that shown below:
Connecting Components
In the main panel, look in the Connections column under the System Contents tab. The interface of each component is displayed graphically as a set of lines; each line corresponds to a sub-interface (wires).
Let's connect the Clock Output interface of the system clock clk_0.clk to the Clock Input interface of the NIOS II processor, nios2_qsys_0.clk: click on clk_0.clk and follow the line to its intersection with nios2_qsys_0.clk. Where compatible interfaces' lines cross, a circle appears: an empty circle indicates the interfaces are not connected; clicking the circle toggles the state.
In a similar manner to the example above, complete the Qsys interconnect according to the following outline:
- Clocks
- Connect all Clock Input interfaces (except clk_0.clk_in) to the Clock Output interface of the system clock, clk_0.clk.
- Resets
- Connect all Reset Input interfaces (except clk_0.clk_in_reset) to the Reset Output interfaces of the system clock, clk_0.clk_reset and the NIOS II JTAG debug module nios2_qsys_0.jtag_debug_module_reset. Note that this can be done automatically by going System | Create Global Reset Network.
- Bus Interconnect
- Connect all Avalon Memory Mapped Slave interfaces to the Avalon Memory Mapped Master interface of the NIOS II processor, nios2_qsys_0.data_master. Also connect the NIOS II instruction master to the SDRAM slave.
Interrupt interfaces are hidden by default. Right click anywhere in the System Contents and go Filter | All Interfaces. In the IRQ column, connect all Interrupt Sender interfaces to the NIOS II Interrupt Receiver interface, nios2_qsys_0.d_irq.
Look in the Export column. This shows the interfaces (wires) that are exposed in the root module of the Verilog hierarchy that your project represents. Clicking once exports the corresponding interface (press the Enter key to confirm). Ensure clk_0.clk_in and clk_0.clk_in_reset are exported. Also export all three Conduit (Endpoint) interfaces.
Bus Configuration
In the main panel, look in the Base and End columns under the System Contents tab. These show the memory-mapped address ranges for each slave in your system. You need to partition the address space to ensure these ranges do not overlap.
Ensure the Base address of the SDRAM is set to zero (corresponding to the NIOS II reset vector) and click the padlock to lock it there. Now click System | Assign Base Addresses to perform the partition automatically.
Generation
Click the Generation tab and then click Generate. This produces the Verilog hierarchy represented by your system, including the necessary interconnect logic to make the connections you specified.