ECAD and Architecture Practical Classes
Quartus Project Configuration
Setup
Navigate to hello_world | synthesis in your project directory:
- hello_world.v
- The root module of the hierarchy represented by your Qsys system.
- hello_world.qip
- Describes the files implementing the Verilog hierarchy generated by a Qsys project.
Go Project | Add/Remove Files in Project..., click ... by File name:, find and select hello_world.qip (you may need to change the file type) and click Add.
Also add your synchronisation module from Lab 1. Finally, click OK.
Timing
Looking at the SDRAM specification shows it requires a clock frequency of at least 100MHz. Looking at an Altera tutorial shows there is about 3ns latency between the SDRAM controller on the FPGA and the SDRAM memory itself elsewhere on the board. We will thus need two clocks at 100MHz: one for the system on the FPGA and one for the SDRAM. For the latter, we also need to adjust the clock signal to compensate for the latency between the SDRAM and its controller.
Add a Phase-Locked-Loop (PLL) with two output clocks at 100MHz, setting the Clock phase shift of one to -3.00ns (change units from deg to ns).
Instantiation
Open toplevel.sv. Instantiate the PLL you created above, using CLOCK_50 as the input clock and connecting the shifted clock to DRAM_CLK. The non-shifted clock should be used for everything else and we suggest you call is clk.
Use your module from Lab 1 to synchronise the buttons and use one for reset. Note that the reset to the Qsys module is inverted - it is called rst_n and the _n means negated. The buttons are also inverted (go low when you press them) so assigning a synchronised button to rst_n without inverting anything is appropriate.
Back in Qsys, go to the HDL Example tab to show a partially complete instantiation of the root module for your system. Click the Copy button and paste the example code into toplevel.sv. Complete the example; the result should look something like the following:
Compilation
Now compile your Quartus project and program the tPad as you did in Lablet 1.1.