Computer Laboratory

ECAD and Architecture Practical Classes



  • What is contained in a ".qsf" file and why does the synthesis tool need this information?
  • Why is it important to check the Fmax of the final design?
  • Why do we often simulate designs before synthesising them?
  • Which of the exercise options did you complete?
  • How many clock cycles does your TTC software multiplier take to receive 13, 19, multiply them and then produce the result?

Ticking Criteria

  • You need to correctly answer the above questions and provide them in a written form.
  • One of the options from the first part is implemented according the expected behaviour.
  • Your TTC software multiplier program, when run, will compute the following multiplications: (3*1), (3*10000), (13*19), (13*0).
  • You must give a live demonstration of your solutions (running on hardware for the first part and running in simulation for the second part.
  • Your SystemVerilog and assembler code needs to be cleanly formatted and commented
  • The following header must be added to all SystemVerilog code submitted:
        // ECAD & Architecture Practical Class - Exercise 1 - Introduction to synthesis and simulation
        // Your name
        // Your college
        // Your CRSid
        // Date

Ticking Procedure

  1. Give a live demonstration of the option of your choice and your multiply program in simulation to one of the demonstrators.
  2. Show your work and answers to the questions (on screen or paper) to one of the demonstrators. They will award you with a tick if the work is up to standard.
  3. Print out your final work and add it to your portfolio to be submitted as instructed in the Head of Department Notice.

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