ECAD and Architecture Practical Classes
IntroductionThis this lab you will be implementing Conway's Game of Life on the DE2 board. The DE2 board will be running a prebuilt MIPS soft-core processor together with renderer code that you will write. You will also produce the MIPS assembler to implement the Game of Life cellular automaton.
New instructions that have been tested (update 24/10/2007)Begin by downloading the Quartus Archive file from the Tiger "MIPS" page. When you open this file in Quartus you will be asked where you'd like to place the project, so select a suitable directory (e.g. U:\game_of_life on the PWF). Note that this project has incremental compilation enabled which works just fine on the PWF, but is not licensed on the web edition of the tools. If you turn off incremental compilation, then it should compile just find on the web edition.
This contains a working Quartus project that will form the basis of this lab. Open the project in Quartus by double-clicking on life.qpf. If you explore the project using the Files tab in the Project Navigator you will find several Verilog files. The files located within the directory Tiger make up the processor. The files mouse.v and mouse_logic.v form the code that talks to the mouse and returns movement data. The only signals that you will need to use are the x, y and left output signals from the mouse_logic module. The x and y values give the position of the cursor on the screen, with the origin at the top-left. The "left" signal changes state each time the left mouse button is pressed. Important:it does NOT go high when the button is pressed, and low otherwise, it is a two-phase signal that changes state each time the button is pressed life.v is the top-level module in this project, and the renderer has the same basic layout as the previous lab. The majority of the other Verilog files have been auto-generated using SOPC Builder (see the description below). The only other file that may be of interest at this point is the initial.mif file, this contains the data to be loaded into the frame buffer when the chip is programmed.
N.B. when you open up the programmer, you may find the programming file is set to something like "Z:\...\life.sof" if this happens, change this to the life.sof file in the working directory by double-clicking on it and selecting the correct file from the dialog.
OptionalFor those who are interested, download the shell file from the Tiger "MIPS" page instead. This contains the project without the SOPC component or incremental compilation set up. To set these up you will have to follow the respective tutorials. This will take slightly more time, but would serve as a good introduction to some of the tools available. Ensure you complete the SOPC tutorial first, followed by incremental compilation.
Warning: SOPC Builder used not to work on the PWF machines but we now believe does work though it could do with more testing. If you would like to try SOPC builder, see the tutorial for details.
SOPC BuilderSOPC Builder (System On a Programmable Chip) is a tool that is provided as part of Quartus to assist in producing larger systems consisting of several components sharing a common bus. It is accessable via Tools | SOPC Builder. You will not be required to use this in order to gain the tick, since the component has already been created for you. For those of you who are interested, there is a brief introduction to SOPC Builder here.
Incremental CompilationA full compilation of this project takes roughly 10-15 minutes to complete. In order to reduce the time you spend sitting around twiddling your thumbs waiting for it to compile, this project has been set up to make use of the incremental compilation feature available in Quartus. This essentially involves splitting the project into several logical partitions, and assigning each of these a specific region of the FPGA to use (called a LogicLock region). A full compile is performed, and then subsequent compiles will only re-synthesise and fit those partitions that contain changed source code. The project currently has 2 partitions, one for the entire project, the other holding the processor only. Thus, if no changes are made to the processor, then this will not be re-compiled each time, significantly shortening the compile time. Those who are interested further in incremental compilation and its uses will find Altera's documentation helpful.
Additionally, the physical synthesis setting is set to "fast". This reduces the compile time to a few minutes, at the expense of producing less efficient designs. The design currently is set up to run off a 25MHz clock, since a 50MHz one gives a few timing warnings when it is compiled. After the labs have been completed, you may wish to try changing it back to a 50MHz clock and sorting out the timing issues. Note you will have to change a few parameters in the mouse module that relate to wait states. If you decide to have a go at a 50MHz clock then it is best to set the physical synthesis setting back to "normal" or even "extra" to allow for more optimisation during compilation. To do this, go to Assignments | Settings and on the left hand tree view, select Fitter Settings | Physical Synthesis Optimizations. At the bottom, under Physical Synthesis Effort select Normal and click OK. Only change this if you need to, as it will push the compilation time up. Once you have the project set up, compile it once to check that it is working, then proceed to the next step.
DebuggingAlso included in the toolset is a file serialio.S. This contains various routines for reading from and writing to the JTAG port on the processor, allowing you to output information that may be useful for debugging. Each function is commented in the file, together with what registers each uses. The file is included via a c-type "#include" statement, which has already been added to the main assembly file that you will be using (life.S). The functions are called via the standard
In order to view the output, you need to start the JTAGTerminal program from a command line (this will not work from within
the IDE). The JTAG Terminal takes 1 argument which is the cable name you will be connecting to. This can be found in the drop-down box
in the MIPS Communication Server, and looks something like "USB-Blaster [USB-0]". I.e. you would start the program up using a command
of the form
GDB is also available for debugging. In order to start a debugging session with GDB you can use the debug.bat batch file. On the command line (not in the IDE), while in the Toolset directory, run debug.bat prog.elf (once you've built your program). You will be presented with a GDB prompt. Type help to get a full list of possible commands. The ones of particular interest will be: