Computer Laboratory > Teaching > Course material 2009–10 > ECAD Labs > Manchester Baby

  The Manchester Baby

The Manchester Baby was the world's first stored program computer, running its first program in June 1948. It was designed as a prototype to the Manchester Mark I and to test CRT memory. With only 7 instructions the Baby was only useful for small applications such as basic mathematical functions. (Cambridge's EDSAC took the title of being the first practical stored-program computer less than a year later).

The Baby had a 32x32bit William's Tube memory and two registers, a 32-bit ACCumulator and a Control Register (CR) which held the address of the current instruction (CI) (the equivalent of a program counter) and the instruction itself (PI).

Further information about the Baby can be found at Digital60, a website to celebrate the Baby's 60th anniversary, or more in-depth at the webpages of the 1998 Baby Programming Competition

  Acknowledgements and Licences

Creative Commons License Manchester Baby in SystemVerilog by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.

Creative Commons License Manchester Baby simulator in Java by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.

Creative Commons License BabySNPtoV Utility by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.

This software was written in July 2009 whilst working on an Altera-sponsored internship. I am grateful to authors of the Game of Life lab session render code as this formed the base of that used in the SystemVerilog implementation and to Simon Moore for his help and advice.

The programs supplied with these tools are the work of their respective authors, and either came from here, as part of M1SIM (see below), or in the case of FIB, from Simon Moore's Computer Design lecture notes.

  SystemVerilog Implementation

A SystemVerilog implementation of the Baby is available as a zip of the source files or as a Quartus archive file. The main module of interest is as this is the module that actually implements the processor. The rest are mainly concerned with rendering the output, handling the clock and so on. As the Baby is such a basic machine, most of the implementation is simple enough that it could be comprehended by a part IB student with reasonable ease.

Controls for the SystemVerilog implementation on an Altera DE2 board are as follows:

  • Switches 17-15 select which of the three programs to load, with higher numbered switches overriding lower numbered ones.
  • Switches 2-0 select the speed of the machine - 7 speeds + stop with 111 being the fastest, 001 being the slowest and 000 being stopped.
  • When the machine is stopped KEY3 advances the machine 1 step of the 4-step cycle and KEY2 advances the machine a whole cycle.
  • KEY0 resets the machine back to the Initialisation stage. The purpose of this stage is to load the program into memory, and it behaves similarly to the normal processor execution. Once the program is fully loaded (after 32 cycles, speed controlled as above) the machine will start executing the program.
  • Both the seven-segment LEDs and the VGA output give an indication of the state (Initialising, Running or Stopped) of the machine, and when running which step of the cycle is currently being carried out (see below). The VGA display also displays the main memory on a William's Tube, the ACCumulator register, the first 5 bits of CI and the corresponding signed hexadecimal values.

  Java Simulator

A Baby simulator, written in Java, is available for download here. The source file is also included for those interested. The simulator runs on snapshot files, examples of which are included. If you would like to write your own Baby programs read the relevant section below.

The simulator displays the Williams tube output and the corresponding values of each line in signed hex. A delay of 1ms is added to each instruction execution to make the simulation more realistic.

  IMPORTANT - Baby Number Representation

Please note: the Baby represents binary with the least significant bit on the left (opposite to the modern convention of it being on the right). The William's tube outputs in the Java/SystemVerilog implementations therefore use this representation, but all hex values on the display are written using the modern conventions. Snapshot files should be written with the LSB on the left, but these are automatically revesred when read in, handled internally using the modern conventions and then reversed again on output.

  Notes on both implementations

Both implementations of the Baby have a very similar structure. They aim to replicate the general behaviour of the Baby as close as is reasonably possible. Both are based around a 4-step cycle, which sequentialises the behaviour of the SystemVerilog implementation, making it match the Java simulator quite closely:

  1. Increment CI
  2. Load instruction addressed by CI into PI and decode
  3. Execute the instruction, set flags for memory/CI/ACC updates
  4. Write the updates to the relevant memory line or register

Listed below are the key differences between the implementations and the real Baby, and also how the two implementations differ from each other:

  • The idea of using snapshot files for inputting the program is simply a modern convenience. The real Baby had a simpley keyboard which allowed the user to set the values of each memory line and register. This means that the Initialisation stage on the SystemVerilog implementation and the constructor in have no counterparts in the real machine. Similarly, the SystemVerilog and Java implementations assume the initial register values are zero, which would usually, but not necessarily, be the case on the real Baby.
  • If the result of a TEST instruction was to skip the next instruction, the real machine would set a flag and increment CI twice at the start of the next cycle. For ease the new implementations will increment CI once in the write-back stage, depending on the TEST result, and then always in the first stage of the following cycle.
  • Due to the way the machine updated the Control Register (CI and PI), bits 13-15 of CI becoming anything other than 000 could cause unexpected behaviour which is not replicated in either implementation.

  Writing your own Baby programs

A good guide to programming the Baby can be found at the 1998 Programming Competition webpage. Another Baby simulator, M1SIM by Andy Molyneux comes with a handy Baby assembler, allowing you to write in mnemonics (such as JMP 5 and SUB 10) and have them converted into snapshot files automatically. The simulator, assembler, instructions and a number of examples can be found in available here. Please note that the simulator itself is written for DOS and requires a full-screen command prompt, which can only be achieved in Vista using a utility such as DOSBox.

If you want to run your programs on the SystemVerilog implementation then you need to create a SystemVerilog module representing the snapshot file. A Java SNPtoV utility has been created to aid this conversion. You can download the program and source here. Once you have created the SystemVerilog module, you should add it to your project and adjust the lines in that instantiate the progNAME modules with registers prog1, prog2 or prog3 (the programs that are selected by switches 15-17) accordingly.