ECAD and Architecture Practical Classes
The Manchester Baby was the world's first stored program computer, running its first program in June 1948. It was designed as a prototype to the Manchester Mark I and to test CRT memory. With only 7 instructions the Baby was only useful for small applications such as basic mathematical functions. (Cambridge's EDSAC took the title of being the first practical stored-program computer less than a year later).
The Baby had a 32x32bit William's Tube memory and two registers, a 32-bit ACCumulator and a Control Register (CR) which held the address of the current instruction (CI) (the equivalent of a program counter) and the instruction itself (PI).
Manchester Baby in SystemVerilog by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.
Manchester Baby simulator in Java by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.
BabySNPtoV Utility by Richard Leivers is licensed under a Creative Commons Attribution-Non-Commercial-Share Alike 2.0 UK: England & Wales License.
This software was written in July 2009 whilst working on an Altera-sponsored internship. I am grateful to authors of the Game of Life lab session render code as this formed the base of that used in the SystemVerilog implementation and to Simon Moore for his help and advice.
The programs supplied with these tools are the work of their respective authors, and either came from here, as part of M1SIM (see below), or in the case of FIB, from Simon Moore's Computer Design lecture notes.
A SystemVerilog implementation of the Baby is available as a zip of the source files or as a Quartus archive file. The main module of interest is babyproc.sv as this is the module that actually implements the processor. The rest are mainly concerned with rendering the output, handling the clock and so on. As the Baby is such a basic machine, most of the implementation is simple enough that it could be comprehended by a part IB student with reasonable ease.
Controls for the SystemVerilog implementation on an Altera DE2 board are as follows:
A Baby simulator, written in Java, is available for download here. The source file is also included for those interested. The simulator runs on snapshot files, examples of which are included. If you would like to write your own Baby programs read the relevant section below.
The simulator displays the Williams tube output and the corresponding values of each line in signed hex. A delay of 1ms is added to each instruction execution to make the simulation more realistic.
Please note: the Baby represents binary with the least significant bit on the left (opposite to the modern convention of it being on the right). The William's tube outputs in the Java/SystemVerilog implementations therefore use this representation, but all hex values on the display are written using the modern conventions. Snapshot files should be written with the LSB on the left, but these are automatically revesred when read in, handled internally using the modern conventions and then reversed again on output.
Both implementations of the Baby have a very similar structure. They aim to replicate the general behaviour of the Baby as close as is reasonably possible. Both are based around a 4-step cycle, which sequentialises the behaviour of the SystemVerilog implementation, making it match the Java simulator quite closely:
Listed below are the key differences between the implementations and the real Baby, and also how the two implementations differ from each other:
A good guide to programming the Baby can be found at the 1998 Programming Competition webpage.
Another Baby simulator, M1SIM by Andy Molyneux comes with a handy Baby assembler, allowing you to write in mnemonics (such as
If you want to run your programs on the SystemVerilog implementation then you need to create a SystemVerilog module representing the snapshot file.
A Java SNPtoV utility has been created to aid this conversion.
You can download the program and source here.
Once you have created the SystemVerilog module, you should add it to your project and adjust the lines in baby.sv that instantiate the progNAME modules with registers