Principal lecturer: Dr Simon Moore
Taken by: Part IB, Part II (General), Diploma
Past exam questions
The aims of this course are to introduce the hardware/software interface models and the hardware structures used in designing computers.
The first seven lectures are concerned with the hardware/software interface and cover the programmer's model of the computer. The
last nine lectures look at the hardware inplementation issues at a register transfer level.
This is a 16 lecture course lectured by Simon Moore. The course is split into two parts.
Part I - The Hardware/Software Interface
The first part of this course covers the programmer's model of the computer.
- Introduction to the course and some background history
- Historic machines: EDSAC vs. Manchester Mark I
- Introduction to RISC processor design and the MIPS instruction set
- MIPS tools and code examples
- Operating system support + memory hierarchy & management
- Intel x86 instruction set
- Java Virtual Machine
- Memory hierarchy (caching, etc.)
Part II - Hardware Structures
The second part of this course looks at hardware implementation issues
at a register transfer level. Note that this updated schedule of lectures is
slightly different from the published syllabus.
- Executing instructions - an algorithmic viewpoint
- Pipelining & data paths
- MIPS processor design part I
- MIPS processor design part II
- Internal and external communication
- Many-core processors
- Data-flow processors & comments on future directions
Code from lecture 9
The following Java code is presented in lecture 9:
- memory.java - memory class
(common to both versions)
- isseg1.java - top level
class for design 1
- processor1.java -
processor class for design 1
- isseg2.java - top level
class for design 2
- processor2.java -
processor class for design 2
Note that the amount of white space has been reduced (particularly
left indentation) to make it fit a slide format. This is probably not
desirable in general.
I would be interested in any improved versions (that don't increase
the length by much). If somebody elaborates on design 2 to include
all instructions (mainly requires extensions to the decoder), then I
would be interested in that too.
- Harris, D.M. & Harris, S.L. (2007). Digital Design and Computer Architecture. Morgan Kaufmann.
- Hennessy, J.L. & Patterson, D.A. (2002). Computer Architecture: A Quantitative Approach. Morgan Kaufmann (3rd ed.).
- Hennessy, J.L. & Patterson, D.A. (1998). Compuer Organization and Design. Morgan Kaufmann (2nd ed., as an alternative to
Handouts and workshops
- Copies of the handouts will be made available at the first lecture and subsequently from the Student Administrator in the William
Gates Building. Please note that the handouts only give an outline of the course. Annotations and additional examples are given in
- If paper copies of the handouts are not available for some reason, the PDF notes for
part 1 and
part 2 are
available for people in the cam.ac.uk domain.
- Architecture workshops for Part IB students (not taken by Diploma and Part II(gen.) students).
- Lecture 5, slide 11 - the multilevel page tables have 1024 entries
rather than 512 entries, and the right most set of tables is the "2nd
level page tables" and not the "1st level page table".
There are 2 lab exercises (ECAD & Architecture workshops 1-3 and 4-6) taken by Part IBs only. There are two tripos questions for
Part IBs and Diplomas this academic year.