psfig

Fairisle Port Controller
Design and Ideas

Mark Hayter and Richard Black

10th March 1994

The Fairisle Port Controller is designed to be a flexible card providing the input buffering for the Fairisle switch and to allow for investigations of queueing and network management. There are three versions of the hardware. The original version, FPC1, was used for initial testing of the hardware and software for the project, only five were built and they gained a number of patches including connector changes. The FPC2 forms the basis of the network built for the Fairisle project itself, and only requires patches if it has its processor upgraded or if it runs the Xi6 design (see later). The FPC3 is built as part of the BT supported Fairisle follow-on project and contains the updated hardware to aid experimental work.

• The Port Controller
• The cell buffer memory
• The xilinx DMA controller
• Status and Control
• Programming the xilinx chip on the port controller
• The network interface
• The Podule Bus
• The Identity PROM
• The interrupt handler
• Links on FPC2
• Links on the FPC3
• Patches for FPC2 and Xi6
• About this document ...