The FPC1 and FPC2 have a parallel network interface. This is normally used to connect a daughter board on FPC2 to interface to the transmission medium, but a Universal Fairisle Connector may also be used. The interface is byte wide, and is asynchronous. The connection has two parts, one for transmission and one for reception, as detailed in table 7. A separate connection to the daughter board joins to two 50R coax connectors which are mounted on the main PCB for stability.
Table 7: Port Controller network interface
Data is extracted a byte at a time on the transmit side by
strobing the Readbar line
low. The start of a cell is marked by having the SOC bit set, the data
which accompanies this is undefined. Following the SOC are the 52 bytes
of the cell. If there is no data available then the Emptybar line
will go low, and reads are undefined. Emptybar goes low as the last
valid byte is being read. The transmission system should read this
stream of bytes and convert them into the form required by the link,
to maintain compatibility with the emerging link standard it may
inset the HEC byte after the first four bytes have been
sent
. The
reception system should convert the form on the link back into the SOC
and bytes form, which it should supply bytewise when the read request
is strobed on the receive side. The port controller expects to receive
in the same form as it sent, so the simplest link may be provided by
cross connecting the transmit and receive connections of two port
controllers using ribbon cable; experiments suggest that the ribbon
cable should be less than 40cm. Alternatively a serial link can be
used by plugging in a TAXI transmission card which provides a link
based on twin coax that can run a few hundred Metres.
Another possibility is for a parallel connection to be made to the
interface card of a host machine. The timing details for the reads and
empty signal are as for a Am7200-35 CMOS fifo, with a 45ns read cycle,
35ns read access and empty going low 30ns after the read cycle of the
last byte is initiated. This may be modified to the faster -25 fifo.
The FPC3 has the TAXI transmission system on the main PCB. No other transmission interface can be used. There are problems with some of the batches of synchronous fifos used on the FPC3 transmission system. Fifos with date stamp of 9230 are not affected. Fifos with a date stamp of 9318, 9338 or 9343 require 22pF capacitors on the clock lines of the side of the fifo which is driven by a TAXI chip.