Cells on the port controller consist of a 4 byte header and a 48 byte payload. In addition a two byte routeing tag must be prepended to cells injected into the switch fabric. The input buffer on the port controller consists of 128k of fast SRAM, organised as 32k 32 bit words. This is logically divided into 2048 cell buffers, each of 16 words. The cell data occupies words 2 to 13 (inclusive) of a cell buffer, use of the other words depends on the version of the control xilinx used. Internally when data is moved as 32 bit words a little-endian format is used, ie low numbered bytes appear in the low bits.
The switch routeing information consists of two bytes. In all cases the least significant bit is the ``active'' bit and is used to indicate the start of a valid cell. The first byte is used to select the switch output to be used, and is described in the Fabric design document. The second byte, known as the ``portc route byte'' is used by the device on the output of the switch to perform internal routeing. The format used by the port controller is shown in table 1, the documentation for the DAN ATM devices and CPU node should be consulted for details for other devices. Note that since the routeing bytes are discarded on the way through the fabric and port controller the spare bits cannot be used to send information.
Table 1: FPC Port Controller Route byte