The Fairisle Switch is based around a simple switch fabric with all the processing being done in the port controllers. The port controller consists of two parts. The first is a processing unit based around an ARM RISC processor. The second section consists of buffer memory and a DMA engine. Figure 1 shows an overview of the port controller, the lower half forming the processor section, and the upper the network section. The transceiver section, containing the encoders and drivers for the line, is a plug in card on the first two versions of the port controller, and is included on the main board in version three.
Figure 1: Port controller layout
The processing section of the port controller has an ARM processor and runs the Wanda micro-kernel. The current boards can have either 1 or 4 Mbytes of dynamic memory and 128, 256 or 512k bytes of ROM. The card includes an Acorn podule bus to allow the addition of other network interfaces. In addition to the standard ARM version of the Wanda kernel there is a hand crafted interrupt routine to deal with the queueing of cells. Cells are only buffered on the input to the fabric - the processor has no control of the fabric output. The port controller includes an identity PROM, which is used to give each port controller a unique id.
The network section of the card contains 128k bytes of static memory, buffer fifos and the xilinx control chip. The static memory is used for cell buffering, and resides in the memory mapped I/O space of the processor. The xilinx arbitrates access to this memory between the processor, transmission to the fabric and reception from the network. The fifos are between the port controller and the transmission system to decouple the different transfer speeds.
The port controller is a double hight extended depth eurocard which
plugs into the Fairisle Backplane
. The backplane links port controllers with the fabric
card and provides power.
The main control hardware is contained on a xilinx FPGA. This is programmed by the processor at kernel initialisation time. Over the period of the project many versions of the xilinx hardware have been produced and the hardware/software balance has been investigated. There are three main versions of the xilinx design in general use. For the FPC2 the two designs are known as Xi3 and Xi6. For the FPC3 the design is Xi5. These three are described in separate documents.