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Cell: dyndata4 | © Simon Moore, 1997 | |||||||||||||||
Used Bycontdyndata4_v1 |
Subcells Used2 x incD2_v18 x inv3 8 x power 4 x redZZor2_v2 4 x redor2_v2 8 x select2_aoz_v2 8 x simplebuf |
Notes4 bit (dual rail data) slice of a 2 stage self-timed pipeline with dynamic incrementer. Data inputs come either from the chip wide input data path (metal 1, left) or fed back from the data output of this circuit (metal 2 loop) and are selected using the select2_aoz_v2 cells on the left hand side. There is a dynamic incrementer between the first and second pipeline stages (made of two incD2_v1 cells). |
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