Used By

Subcells Used

Notes

4 bit (dual rail data) slice of a 2 stage static self-timed pipeline. Data inputs come either from the chip wide input data path (metal 1, left) or fed back from the data output of this circuit (metal 2 loop). There is a dynamic logic incrementer between the first and second pipeline stages. Most of the details are in gendata4 since this cell just adds a couple of 4 input nand gates at the top.

Key

	metal 2
	metal 1
	polysilicon
	via or contact
	N+
	P+
	N well