contents | 1-overview | 2-background | 3-results summary | 4-results details | 5-deliverables | 6-dissemination | 7-conclusions
Improving Smartcard Security using Self-timed Circuit Technology - Simon Moore, Ross Anderson, Markus Kuhn (University of Cambridge)
Fourth ACiD-WG workshop, G
Self Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems - S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P.Robinson,
International Conference on Computer
Design,
ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smard Cards - Jean-Jacques Quisquater and David Samyde..
In Smart Card Programming and Security (E-smart 2001), Cannes, France, LNCS 2140, pp.200-210. September 2001.
Protecting Consumer Security Devices - the next 10 years - Simon Moore, University of Cambridge
In Smart Card Programming and Security (E-smart 2001), Cannes, France September 2001
Bundled-Data vs Clocked ASIC Design - S.W.Moore, G.S.Taylor, R.D.Mullins and P.Robinson,
10th UK Async. Forum, July, 2001.
Security Engineering – Ross Anderson
John Wiley & Sons, Inc. ISBN 0-471-38922-6
Point to Point GALS Interconnect - Simon Moore, George Taylor, Robert Mullins, Peter Robinson
Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2002
Improving Smart Card Security using Self-timed Circuits - Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, George Taylor
Computer Laboratory, University of
Cambridge ASYNC 2002
Optical Fault Induction Attacks - Sergei Skorobogatov, Ross Anderson. University of Cambridge, Computer Laboratory
Workshop on Cryptographic Hardware and Embedded Systems (CHES 2002) Redwood City, USA. August 13-15, 2002
Side Channel Cryptanalysis - Jean-Jacques Quisquater and David Samyde. UCL
Invited talk in SEcurité de la Communication sur Internet (SECI 02). Tunis, Tunisia. September 2002
Eddy current for Magnetic Analysis with Active Sensor - Jean-Jacques Quisquater and David Samyde..UCL
Proceedings of Esmart 2002 3rd
edition.
SPA - A Synthesisable Amulet Core for Smartcard Applications - L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside and S. Temple
Proceedings of the Eighth
International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). Pages
201-210.
Chain: A Delay-Insenstive Chip Area Interconnect - W. J. Bainbridge and S. B. Furber
IEEE Micro, Volume 22, Number 5, Pages 16-23, September/October 2002. Published by the IEEE Computer Society.
On a New Way to Read Data from Memory - David Samyde(1), Sergei Skorobogatov(2), Ross Anderson(2) and Jean-Jacques Quisquater(1)
SISW2002 First International IEEE Security in Storage Workshop
(1): Université catholique de Louvain, UCL Crypto Group Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium
(2): Computer Laboratory, JJ Thompson Avenue, Cambridge CB3 0FD, England
The following papers have been submitted and/or accepted
SPA - A Synthesisable Amulet
Core for Smartcard Applications - L. A. Plana,
P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside, S. Temple and Z.
C. Yu
Journal of Microprocessors and Microsystems. Special Issue on Asynchronous
System Design, 2003.
An Investigation into the
Security of Self-Timed Circuits - Z. C. Yu,
S. B. Furber and L. A. Plana
Submitted to the Ninth International
Symposium on Asynchronous Circuits and Systems. To be held in
Balanced Self-checking
asynchronous logic for smart card applications
by University of Cambridge and Gemplus CSG,
Journal of Microprocessors and Microsystems. Special Issue on Asynchronous
System Design, 2003.
Towards security by design by Gemplus CSG and the University of Cambridge, submitted to CHES 2003
R.J. Anderson and S.W. Moore, Microprocessor Resistant to Power Analysis, International application number: PCT/GB01/00311, International filing date 26 January, 2001.
contents | 1-overview | 2-background | 3-results summary | 4-results details | 5-deliverables | 6-dissemination | 7-conclusions