3 Results – summary

After three years, the project has produced the following:

1. A prototype XAP chip. As well as the intended secure XAP processor, the test chip contains, for the purposes of comparison, three further asynchronous XAP processors, with different design styles, and a synchronous one.

2. A prototype of the MIPS4Ksc™ 32 bit processor (SmartMIPS) variant whereby the Multiply & Divide Unit (MDU) has been redesigned to integrate both the clocked version and the fully asynchronous one. The latter has been developed in close cooperation with the TIMA lab (Grenoble, France).

3. A prototype 32 bit completely asynchronous ARM processor, built in a new variant of asynchronous logic.

4. A new design style of failure-evident asynchronous logic– secure dual rail.

5. A set of tools for checking designs for some types of information leakage at the design stage, thus reducing the time and cost of prototyping.

6. A prototype operating system that uses hardware security features to allow multiple applications on the same card in a secure manner.

7. A new algorithm – elliptic point counting – for rapid generation of crypto keys, capable of being run on a smartcard, for potential future applications.

8. A set of results, spread across the asynchronous design space, showing where asynchronous design can contribute to higher levels of security..

9. The development of a new family of semi-invasive attacks, in which one can either induce revealing faults in chips or read out memory contents directly, and using either lasers of induced electromagnetic fields.