Computer Laboratory

Picture of Hongyan Xia

I am a fourth year PhD student at the University of Cambridge Computer Lab, supervised by Prof. Simon Moore within the Computer Architecture group. My research looks into low-cost, low-latency memory safety for embedded systems as well as temporal memory safety under the CHERI architecture.

I also completed the MPhil degree in the CompArch group before my PhD, focusing on extending the RISC-V architecture with tagged memory for various sorts of debugging and acceleration. Even before that, I studied Electronic and Computer Engineering in a joint program by Huazhong University of Science and Technology and the University of Birmingham.

As a researcher I am generally interested in embedded systems, real-time operating systems and novel architectures for security. Outside research hours I play some first person shooters, enjoy cycling and am now learning German. Anyone welcome to help me practice the language!

Projects

A Real-Time Operating System, CheriRTOS: https://github.com/Jerryxia32/cherios/tree/cheri-n32
A dlmalloc-based non-reuse heap memory allocator: https://github.com/Jerryxia32/dlmalloc_nonreuse/tree/lite

Publications

  • Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert Norton, Thomas Bauereiss, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel W. Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, and Simon W. Moore. CHERI Concentrate: Practical Compressed Capabilities. In IEEE Transactions on Computers, 10.1109/TC.2019.2914037, IEEE, 2019.
  • Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, MichaelRoe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore, and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices. Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD). Orlando, FL, USA, October 7-10, 2018.
  • Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey Son, and A. Theodore Markettos. Efficient Tagged Memory. Proceedings of the 2017 IEEE 35th International Conference on Computer Design (ICCD). Boston, MA, USA, November 5-8, 2017.
  • Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Robert Norton, Stacey Son, Hongyan Xia. Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6), Technical Report UCAM-CL-TR-907, Computer Laboratory, April 2017. Current CHERI ISA specification

Contact

Email: hx242@cam.ac.uk
Phone: +44 (0)1223 763745

Department of Computer Science and Technology
University of Cambridge
15 JJ Thomson Avenue
Cambridge CB3 0FD

Last updated 2018/11/27